It is arguably a provocative title, but going purely off the heading is akin to judging the book by its cover. The institutional note “automagically” landed in my inbox and I had a long, quiet read to process it. I also read all the notes by FundaAI around this, a few other Substack notes, and tried to keep up with the flurry of takes on X.

The now infamous note is largely post-Computex, where we identified optics and power as the major themes as well. Here is our coverage this week:

• 📚 Computex 2026 Debrief

• 🎙️ Computex 2026: Decoding Optics and Power Content

The long and short of it that CPO is coming eventually, as is 800V; nobody denies this, but the controversy is around the when. We’ll focus on CPO today.

The SemiAnalysis claim worth focusing on is that Spectrum-6 CPO is slipping by 2+ quarters due to: (1) an unusual level (>3.5 dB) of optical loss in Spectrum-6 that eats link margin and notably higher than Spectrum-5 that uses a similar port count forcing a redesign, and (2) a yield constraint that causes issues at scale.

We have no way of verifying actual numbers here, unless the reader is the rare case of the one actually working on it. However, technical discussions around these two claims are light, and rebuttals mostly come from the supply chain argument side. There is little dialogue around understanding why this could happen, and if the engineering side holds up.

We will try to fill in this gap today.

This edition of TWiC is presented by … SambaNova

Run frontier models. Skip the GPU rack.

SambaCloud runs MiniMax M2.7, the fastest provider for this model, at 435 tokens per second via API. M2.7 ranks alongside Claude Opus 4.6 and GPT-5.4 on agentic and software engineering tasks, at a fraction of the cost. No hardware procurement, no lead time, no sharding across hundreds of GPUs.

Texas Advanced Computing Center, OVH Cloud, and Hume.ai are already on the platform. If you’re running long-horizon agent workflows in production, M2.7 is available today on SambaCloud’s Developer and Enterprise tiers. Benchmark your workload against your current provider in an afternoon.

👉🏽 Start benchmarking today.

The industry agrees as a whole that scale-out is where CPO lands first. NVIDIA Spectrum-X CPO (Ethernet) and Quantum-X CPO (Infiniband) are slated to enter mass production in 2026. The SemiAnalysis claim is that the Ethernet version is due to slip by 2+ quarters, and is materially important because the Ethernet version ships more volume than the Infiniband one.

Both the increased optical loss and yield issues have their roots in the sub-micron accuracy alignment requirements of optical engines for CPO, and requires a procedure called “active alignment.” It involves optimizing the fiber attach unit (FAU) to the photonic chip across 6 degrees of freedom (position+angle across x,y,z). The alignment is done by actively monitoring the amount of optical power being coupled, and a few degrees of freedom are adjusted till maximum power is coupled.

This has to be repeated for each optical engine in the whole Spectrum-X switch, and is required at several points along the CPO build process. Even a single CPO module can require 100+ active alignment operations from start to finish, each one taking only a few seconds from start to finish in high volume production.

CPO testing is an interesting aspect that deserves its own deep-dive, but key takeaway is that co-packaging an optical engine next to the silicon is notoriously difficult, and the difficulty arises when all of them need to work when attached. Quantum X actually implements CPO differently from Spectrum X as shown in the pictures below.

Quantum-X is designed for routing supercomputing traffic with ultra-low latency. It has a total of 18 optical engines (6x optical subassembly with 3 engines each) to provide 18 ports in an NVswitch supporting Infiniband. Quantum X uses a replaceable module of 3 optical engines that can be swapped out as a whole if any one of the three engines in the module do not work. The complexity of active alignment is limited to just the optical subassembly now. If the yield of each attachment is 95%, the overall yield of the subassembly is 0.95³ = 0.853, or 85.3%.

Spectrum-X handles larger, multi-tenant cloud and Ethernet AI environments and thus requires more port counts, and more optical engines per switch. As a result, the “swappable module” approach does not work for this product line due to sheer lack of space. You can see from the picture that there are 32 optical engines directly co-packaged next to the silicon. A single non-functioning optical engine poses a danger to the entire switch.

Here the math is that if each one has a 95% chance of success, then the chance of all 32 engines being successful is (0.95³²=0.193, or ~19%). This makes it significantly harder to deploy Spectrum-X switches at scale if the yield is so low. If you want ~85% yield like we saw in the 3-engine optical subassembly, the required attachment yield rate skyrockets to 99.5%. There are some counter-arguments floating by to this method.

1. Is the yield really 95%? This number is genuinely difficult to come by, and if based purely on hearsay, is something to take with a grain of salt. The exact yield number matters a lot, arguably to the last decimal point, when you take a power of 32. Hand wavy napkin math does not work here.

2. Failing parts are binned. One post I read argues that the napkin math is bad because optical engines are binned and only functional ones will be attached and therefore the failure rate cannot possibly be that high. Yes, failing parts are binned, but the actual failures come during/after the attach process. As a result, there is no way to avoid the power of 32.

Most of the commentary on this matter has been a rebuttal on the basis that the bottleneck is on the supply-side, and not the demand side. Lumentum’s comments at the Mizuho conference also stated how much demand is waiting for them, if they could only ship. Morgan Stanley released a note with wafer shipments, while acknowledging TSMC yield numbers in SoIC and downstream assembly yield.

Subscribe now

The loss and yield argument makes “qualitative” engineering sense given how Spectrum-X and Quantum-X CPO architectures work, and the crux of the SemiAnalysis argument reduces to finding the right yield number. If there is a fundamental problem with the active alignment process, it is easy to drop half the optical power (which is what 3 dB of loss is) due to misalignment issues; remember that the alignment accuracy requirements are sub-micron for thousands of optical fibers per switch. The loss number itself is within the realm of reason given how sensitive CPO is to alignment issues.

Given how new the industry is to CPO at scale, loss low yield could very well be growing pains as the technology ramps. It is not an unsolvable problem; just one that takes its time as assembly processes for CPO mature. It is entirely reasonable that the alternative while the industry grows to adopt CPO, is NPO.

In the case of NPO, the assembly and packaging process is much simpler because only the optical engine in that NPO module needs active alignment — it is not an exponent-stacking problem like in CPO. This makes it much more conducive to the short/medium term while the CPO production process matures.

What the Street missed in the whole controversy is that whether it is NPO or CPO, the optical content remains unchanged. It is only a question of how the packaging works and the demand for optics is higher than ever, just in different form factors.

But first, Computex is a very large show, and impossible for one person to cover all what it has to offer in any reasonable depth. What I’ll discuss here is by no means comprehensive but I’ll provide a stream-of-consciousness download of the show. I hope you get something useful out of it.

I’ll discuss three major areas:

• Memory

  • The trade

  • HBM4 base die and cooling

  • What would actually break memory

• Optics

  • Why CPO is still early

  • The demos

  • NPO and pluggables

• Power

  • 800V and the conversion chain

  • Delta’s system play

  • When it’s real

  • Moving BBUs out of the rack

By reading this post, you agree to the terms and conditions. Also see the full ethics statement.

If you would like to engage boutique research services for your project, reach out to us.

Contact SemiExponent

Read more

What’s left of my grey cells have been deployed into thinking about interconnects. I have a deep dive piece on how power density is driving up active copper cable use; link below in case you missed it. I believe we’re still in the early phase on this one.

Today’s short post is about a strange contradiction in the argument about what the right laser source for CPO is: a single high power laser, or a wavelength multiplexer, multi-color laser. I believe either one is viable, and we will explore why.

A quick note: I will at Computex 2026 in Taipei next week, and posting might be light while I attend the conference. If you are attending and happen to see me, say hi! 👋🏽

There has been a lot of recent news about Sivers Semiconductor, whose stock has shot up about 2,000% based on their optics business lines for CPO. First thing to note is that their optics business is a minority; their main business is RF, wireless, and phased array antennas for Satcom. I’m surprised more people aren’t talking about them as a potential acquisition target by SpaceX post-IPO – because that’s where their real strengths lie. I’m still not convinced that there’s going to be a Satcom boom post-IPO, so let’s move on.

The other argument I’ve seen is that Sivers’ approach to CPO is inherently flawed, because the use of wavelength division multiplexing (WDM) is worse than using a single powerful external laser.

To explain this further, you should know that there are two schools of thought:

1. Ultra High Power Laser: The idea here is to just create a really powerful laser and keep it external to the rack. Once it reaches the optical engine, you split it up into parallel lanes and modulate each lane with data on a SiPho chip. Coherent showed a 400mW UHP laser, and Lumentum showed an 800mW-1W “Super High Power” (SHP) laser.

2. CW-WDM Laser: The other approach is what folks like Sivers and Ayar Labs are adopting. The light source itself is multi-color from the start with each color having about 50-65mW. Across 8 lanes, that is still 400mW total but you don’t have to split it up at the optical engine. Since you have different light colors, you can modulate each one with data.

But is the WDM approach to CPO really worse than UHP lasers? It is also important to note that Lumentum, often touted for their SHP lasers, also have a CW-WDM laser which is really very good: 8 wavelengths, each up to 100 mW. There is a whole multi-source agreement (MSA) around CW-WDM too.

If CW-WDM is so flawed from the start, why does Lumentum have a product here, and why are they part of the MSA? Note that Coherent is on here too. See the contradiction here?

The real answer is that UHP lasers vs WDM lasers are just two different ways of solving the same problem, and Lumentum is hedging its bets on which architecture will win by having both. Here’s why:

1. The SHP laser approach needs 800mW because it is going to be split up into multiple lanes on the other side. For this, there should be substantial power available for each lane after the split. Let’s take a more “ordinary” UHP laser like the one from Coherent for comparison running at 400mW, single color. Assuming no loss through the channel for simplicity, 400mW gives 50mW per channel across 8 lanes.

2. If you see Sivers’ WDM lasers across 8 lanes, each one has 50mW per channel. No difference at the modulator level compared to the single color UHP laser approach.

You can roughly see how they are equivalent. If you really want to take loss into account, remember that a single UHP laser needs a 1:8 which a WDM approach does not. This adds to the loss budget and requires a higher power laser to start with. WDM instead has to deal with multiplexer/demultiplexer loss. Problems on both sides.

Using a WDM approach means that you can transmit more data on a single fiber, whereas UHP lasers after splitting need different fibers. WDM has bandwidth density that split UHP lasers do not.

What matters is how much laser power is available at the modulator ultimately, and not how much power is available at the external laser source. Running 800mW in a single laser also presents cooling problems, while running 8 lanes at lower power makes thermals easier to manage on a per laser basis.

Higher laser power isn’t a virtue in itself as a lot of commentary on optics makes it out to be. Higher power is good for SNR and BER. But more power also means more heat, which is one thing that lasers explicitly dislike because their lifetimes drop like a rock at higher temperatures. Even if the laser is external to the rack, reliability is one thing that CPO adopters still worry about the most (data from conferences shows that lasers do okay, but no info is available at scale yet).

The real danger to Sivers is not the use of their WDM approach, but instead Lumentum beating them at their own game with higher quality WDM lasers.

Comparison table with reported numbers

Have a great weekend!

This can be done across many axes, with: hybrid bonding for advanced packaging, Unified Bus for memory protocols, near-packaged optics for interconnects and software optimizations overall. We will just focus on the transistor layer here, and address the question: What if the route to leading-edge density did not require a leading-edge transistor at all, but instead came from folding a 7nm-class design back on top of itself until the footprint density rivals a node three years ahead? This is what Huawei calls LogicFolding.

In this post, we will discuss:

• What Tau Scaling and LogicFolding actually are: chasing time as an axis instead of scaling dimension.

• Why hybrid bonding is the hard part: the challenges that decide whether fine-pitch logic stacking actually yields.

• Who builds the bonders: the short, concentrated supply chain and why its geography matters for China.

• How far along China’s own bonder makers are: Where is the current capability, and the gap that still leaves.

• What it means for the US lead: why the same stacking on an EUV-class node widens the gap instead of closing it.

If you need a refresher on hybrid bonding, see earlier post below.

We also have a deep dive on lithography on the Semi Doped podcast. See it on YouTube.

By reading this post, you agree to the terms and conditions. Also see the full ethics statement.

If you are not a paid subscriber, you can purchase just this article using the button below. You can find the whole catalog of articles for purchase at this link.

Buy the ebook

If you would like to engage boutique research services for your project, reach out to us.

Contact SemiExponent

Tau Scaling and LogicFolding

Huawei’s Tau Scaling takes its name from the Greek Letter τ, which represents the delay through a signal path. Historically, making transistors smaller and faster has reduced this delay. But past the 7nm node, making the delay smaller has become increasingly difficult without the use of EUV lithography, which China does not have access to due to export control laws.

Huawei’s solution is practically sound: if you can’t improve the signal delay through the transistor without EUV, why don’t we optimize everything else we can? Their goal is to shrink that delay across four levels at once: the device, the circuit, the chip and the full system.

At the chip level, the way to do this is to take a chip built on a trailing DUV node, like SMIC’s 7nm-class process (incidentally, Huawei has never named the foundry, but everyone assumes it is SMIC). If you can stack logic chips built on this one on top of the other and hook them up, you’ve just doubled transistor density without EUV. Think of it like printing two chips on a napkin, and folding them in half so that they align, and then hooking them up. This is what Huawei calls LogicFolding, and hooking them up requires a packaging technology called hybrid bonding.

By folding chips like a taco, you’ve just reduced the interconnect distance massively, and the unwanted resistance and capacitance that come from longer wiring is dramatically reduced. This makes the silicon run faster with lower delay, and Huawei has effectively made chips faster and denser by stacking them on top of each other.

Huawei reports the Kirin 2026 part, its first LogicFolding product shipping in fall 2026, moving from 155 to 238 MTr/mm² of transistor density (roughly +53.5%), alongside a 41% gain in performance-core power efficiency and a clock bump to 3.1 GHz. The caveat here that many experts are pointing out is that Huawei spent twice the amount of silicon to double the transistor density, which is not the same as using EUV to make denser transistors.

Read more

The rise of power density within a single rack as hyperscalers pack in more GPUs is causing the networking domains to blur. As GPUs per scale-up domain climb, the domain outgrows a single rack and operators split it across racks to keep power density in check. Meta’s Catalina is a prime example where the scale-up domain spreads across racks at lower power density, linked with active copper.

A dense rack like NVIDIA Rubin pulls so much power that many brownfield datacenters (a term used to refer to existing datacenters repurposed for the AI age) cannot host one because the installed racks cannot support the power density. Short of swapping in NVIDIA reference racks as-is, the only way to deploy power-dense hardware is to spread the same GPUs across multiple lower-density racks.

Once power pushes scale-up across racks, passive copper does not have enough reach. But the gap is not wide enough for fully retimed copper with DSPs, which are too power hungry and too high latency, and optics for a few meters is overkill at this networking generation. Active copper fills the gap as a “goldilocks” choice to keep power budgets in check and opens up a new market for AI interconnects.

In this post, we will look at:

• A tour of the interconnect technologies inside an AI datacenter, and where passive copper, active copper, DSP cables, and optics each fit.

• Why rising rack power is forcing scale-up networks to split across multiple cabinets, with Meta’s Catalina as the worked example.

• Which interconnect actually wins the short links between those split racks, and why it turns out to be active copper.

• For paid subscribers, a full competitive teardown of the five vendors fighting for ACC: Semtech, Marvell, MACOM, Ciena/Nubis, and the conspicuous one sitting it out.

By reading this post, you agree to the terms and conditions. Also see the full ethics statement.

If you are not a paid subscriber, you can purchase just this article using the button. You can find the whole catalog of articles for purchase at this link.

Buy the ebook

If you would like to engage boutique research services for your project, click below.

Visit SemiExponent

How AI Racks Move Data Today

All scale-up networking inside NVIDIA racks has been passive copper. The NVLink spine holds roughly 5,000 copper cables. Passive copper, or direct attach copper (DAC), works because its reach inside a single rack covers the generation it sits on. The speeds across three NVIDIA generations:

Hopper, at 100G per lane, gave DAC about 3m of reach which is plenty. Blackwell’s NVLink 5 went to 200G per lane and passive reach fell to about 1.5-2m, but NVIDIA kept the scale-up domain inside the spine by packing all 72 GPUs and the NVSwitch trays into one rack with a copper cable spine, so no link runs far.

Rubin’s NVLink 6 was labeled 400G per lane at GTC 2026, though the industry read is 200G bi-directional. Running a transmit+receive pair at once leans hard on echo cancellation and tightens cable performance demands, but DAC for scale-up is alive and well in Rubin. The added BiDi complexity is handled by the SerDes on the switch silicon, not with external redrivers. Rubin Ultra moves to a mid-plane PCB approach, which is still passive copper.

Scale-out is different: connecting a row of racks needs real reach. It has leaned on active electrical cables (AECs), which drove Credo’s purple cable mania a few years back. Marvell and Astera Labs play on the silicon side; Credo is vertically integrated. As speeds climb, scale-out is migrating to optics, pluggable transceivers first, then CPO for lower energy. For linking datacenters across a campus or beyond, optics is already the mainstay.

Today, a new space for interconnects is emerging as the scale-up domain spans multiple racks; one whose reach is not high enough for pure optics, but also latency and power sensitive for pluggable optics and fully-retimed copper solutions using DSPs. In the 1.6T generation and possibly beyond, this is the space that Active Copper Cable (ACC) is looking to fill.

Why Meta’s Catalina Spans Two Racks

The cleanest scale-up domain is the one that never leaves the rack because passive copper cables without active silicon is cheap, low-latency, and low-power. This is the sole reason why hyperscalers would all keep scale-up inside one rack if they could.

The fundamental problem is that a frontier scale-up rack like NVIDIA’s Blackwell NVL72 uses more power that traditional racks. Once you cross roughly 100 kW in a single rack, you run out of cooling headroom, busbar capacity, or both, and the only move left is to spread out the GPUs across two racks, and run the scale-up fabric between them.

A single GB200 NVL72 draws around 120-130kW in one rack. If most racks in an existing datacenter top out around 60-70 kW per rack, then NVIDIA offers the same 72-GPU domain repackaged as NVL36x2: two cabinets of 36 GPUs at roughly 67kW each. But what if NVIDIA’s customers have their own racks already?

Meta’s Open Rack v3 High Power Rack (HPR) supports 93.5 kW per-rack, and is not suited to directly deploying a single NVL72 GB200 domain within it. At this point, Meta has to either replace all the racks in its existing datacenter with NVIDIA’s reference architecture, or expand the 72-GPU domain across two racks. This latter is what Meta did with its Catalina racks.

Catalina stretches the 72-GPU NVLink domain across two ORv3 HPR cabinets, roughly 36 GPUs and ~67kW each, so both racks sit comfortably inside the 93.5kW power envelope Meta already knows how to cool and power. The Blackwell silicon is NVIDIA’s, but the rack around it is Meta’s implementation so that the cabinet drops into Meta’s existing data halls instead of forcing a new facility build.

The tradeoff lands on the scale-up traffic which has to jump across the split rack domains. In the picture below, you can see a thick bundle of black cables running between the two racks, tying the GPUs on both sides together through the NVLink switches into a single 72-GPU domain. The backend network within each rack is in-rack scale-up. Holding 72 GPUs non-blocking across that split takes 162 cross-rack links (18 ports/NVswitch × 9 NVswitches/rack). The saving grace is reach because the interconnect just has to go to the neighboring rack scale-up, and not run across an entire row like in scale-out networks.

Which Interconnect Wins Multi-Rack Scale-Up

The cable only has to reach the rack next door, which works out to about 3 meters once you allow for slack. That is a short, fixed reach, and at 200G/lane it is enough to rule most of the options in or out.

Passive copper is the first to go. At 200G/lane a plain DAC runs out of reach well short of 3 meters, so it cannot bridge the gap on its own. At the other extreme, a DSP-based AEC reaches far past 3 meters, but it burns around 20 watts per end and carries the latency of a full retimer, which is overkill when all you have to do is cross to the neighboring rack. Pluggable optics runs into the same wall from the other side. It clears the reach and data rate easily, but tens of watts of transceiver power per end is wasteful on a link that only has to span a few meters.

Co-packaged optics is the interesting one. It is the lowest-power and most future-proof option, and NVIDIA is pushing it for multi-rack scale-up in Rubin Ultra. But it is still unproven at scale and ties you to a handful of vendor ecosystems, so it reads as a next-generation answer rather than something to deploy at 1.6T today. CPO is not the only future bet either, as several players are investigating microLEDs and VCSELs for the same short-reach role, though none of these are in large-scale deployment yet.

That leaves the option built for exactly this gap. Active copper cables add a linear redriver, no DSP, which pushes copper out to 3 meters at 200G/lane for just a couple of watts per end. Most of the reach of an AEC, a fraction of the power, and none of the DSP latency.

After the paywall:

• Semtech’s proven design wins, including the marquee platform already running its silicon.

• Why Marvell is every bit as strong in ACC as Semtech, for completely different reasons.

• Why MACOM has the silicon and a standards seat but no ACC wins to show.

• How Ciena bought Nubis for optics and picked up a useful ACC play.

• Why the best-known copper-cable company is sitting ACC out.

Finally, a single table to summarize the competitive ACC landscape.

Read more

Thoughts swimming in my head this week have been entirely around the reality of “Orbital Compute” that Gavin mentioned on the podcast as the next big thing. I just wanted to pen down major themes swirling around this topic, on this week’s TWiC, so that I can revisit this when it becomes The Big Bottleneck™, but hopefully sooner than that.

In other news, I have content published around inference accelerators this week.

• 📚 Inside SambaNova’s Inference Architecture

• 🎙️ Cerebras IPO

Ok, lets get to the space stuff.

There has been a lot going on around the idea of putting datacenters in space. Some newsworthy items in no particular chronological order.

• Startcloud put an Nvidia H100 in space — they have a nice whitepaper worth reading.

• Elon Musk explains on X how datacenters should ideally go to space.

• Google’s moonshot Project Suncatcher explores putting Google TPUs in space.

• Axiom Space is a company working on orbital datacenters.

• Last week, Google and SpaceX are in talks to launch datacenters into orbit.

There’s probably a lot more (leave it in the comments), but 5 bullets will do for now.

With the impeding SpaceX IPO, and the fact that SpaceX has an absolute stronghold in the reusable rocket market while also running datacenters here on Earth, the interest in orbital compute is on the rise. In the interview, Gavin thinks orbital compute is just around the corner — in the 2027/28 timeframe.

The one thing Gavin clears up immediately is — “don’t think about it as a Pentagon-shaped datacenter in orbit.” Instead, he asks you to think about racks in space, not entire data centers floating in sun-synchronous orbit.

Today, the power onboard satellites is around 20 kW, and SpaceX engineers seem to think they can scale that up to 100 kW, which should fit a Blackwell-class rack in orbit. The networking aspect is most interesting. Scale up would remain in copper within the rack for sure, but scale out would use free space optics to connect between orbital racks. Most amazingly, SpaceX satellites today already have the ability to communicate with each other to operate in a mesh using free space optics. This technology isn’t in a lab; it’s actually up in space today.

For the industry itself, running data centers in space means that there are four markets that open up to make this happen.

1) High power free space optics

Connecting racks with free-space lasers isn’t something we do on earth today but constellation operators already have optical satellite links built into them, including SpaceX and Amazon, with Telesat and OneWeb still considering adding laser comms to their satellites. The use of free-space optics would open up an entire segment of the optics industry that isn’t directly involved with AI data centers today such as Tesat (privately held) who are widely known for inter-satellite optical communications, CACI () for their optical terminals for defense work, General Atomics, and others such as Skyloom (bought by IonQ) and Bridgecomm (acquired by Voyager Technologies). If optical comms in space are going to become a thing, only a few people really know how thats done today.

Imagine, if NASA’s Terabyte Infrared Delivery Subsystem (TBIRD) could run at 200 Gbps from Earth to orbit in a system the size of a tissue box, we can connect racks in space alright. I’ve written about this before; see post below.

2) RF SATCOM Companies

If you want to communicate with data centers in space from Earth at scale, the best-known approach is through satellite communication systems operating at Ku or Ka band. Starlink terminals currently use this frequency range and typically require their own satellite terminal to communicate with satellites at sufficient bandwidth.

Companies have tried going direct to cellular, but the bandwidth is usually not high enough. The idea of data centers in space could give second wind to companies working on RF-based SATCOM, especially since their forays into millimeter-wave 5G failed spectacularly.

The key technology here is mmW phased arrays, which use an array of antennas that can be cleverly controlled to form a pencil beam aimed directly at the satellite for maximum data throughput. There’s a GaN angle here too in power amplifiers for satellites. Qorvo, MACOM, Analog Devices are among some companies with this expertise.

Since I have actually worked in this field, I’ve written a bunch of posts about this, if you’re interested.

3) Radhard Specialists

If you’re not familiar with silicon in space, you need to know that silicon has to be space qualified and radiation hardened (Radhard) to work in space. Low Earth orbit deployments are easier from a radiation-hardening perspective because the Earth’s atmosphere shields a lot of radiation. As you move farther from Earth, radiation requirements get much worse.

Aside: I attended a talk by the Voyager mission’s chief engineer at IMS 2025, and he explained how insane it was to design electronics that work in the radiation environment of Jupiter. He was cracked AF and a great storyteller! At 15 billion miles away, the data rate from the Voyager is 160 bytes-per-sec. 😭 A 1-way message takes a day!

The ability to test and qualify parts for space is something a company builds over time, and it typically requires a unique end market. Not every silicon supplier can serve these markets, but defense providers and companies in the satellite space often have this capability, so it is worth watching for. Also, it would be wrong to assume it’s only the GPUs that need space qualification. Every component, from memory up through lasers, PCBs, connectors, and cabling, needs to be qualified for space operation. It’s a different ball game the industry is not entirely ready to play at the scale of orbital datacenters today.

4) Cooling Technology

A common mistake is assuming data centers are naturally suited to space because it’s so cold. Convection is the best way to extract heat from surfaces via air- or liquid cooling, and space naturally has neither.

The only way to remove heat from chips in space is through radiation, which is much less efficient. Cooling is a hard problem for data centers in space, even if liquid cooling is used because heat still has to be radiated away with large radiators to keep the chips cool. The ISS rejects on the order of 70 kW with very large panels, so cooling a single rack in space seems feasible in theory.

The best part is that space, well has “space”. You can make the radiators hundreds of feet in size, so a lot of heat can be exchanged with the cold sink outside kept at a steady 2.7K. NASA studies show radiators can account for more than 40% of total power system mass at high power levels. That is the real reason this is hard.

Some companies to watch for in this space are Sierra Space, Paragon Space Development, Redwire Space, ThermAvant Technologies, and Advanced Cooling Technologies.

If AI is going to space, then I’m going to write deep dives about its various aspects.

Meanwhile, have a good weekend!

• GPUs are packed with HBM, and during inference, the model is sharded across multiple GPUs.

• Groq’s LPUs with their hundreds of MB of SRAM require thousands of chips to run a large-scale model.

• Cerebras can hold up to 44 GB per wafer in SRAM, but requires the problem to be distributed to multiple wafers for large-scale model serving.

SambaNova has a different take on the problem.

What if, instead of a single large Mixture-Of-Experts (MoE) model, you built a composition of many smaller experts, each trained to be competitive with monolithic MoE model experts? Think of 100+ 7B parameter models all doing one thing really well. This is what SambaNova calls Model Bundling, which was the initial motivation for the architectural choices that Sambanova’s hardware is built on.

In this post, we will discuss SambaNova’s 3-tier memory architecture, their Reconfigurable Dataflow Unit (RDU), and how they compare to more recent hardware architectures in the news like Nvidia’s Rubin, Groq LPUs, and Cerebras wafer scale engines.

Specifically, we will discuss:

• The Three-Tier Memory Architecture

• Understanding how RDUs work

• Scaling up to the rack level

• Where SambaNova fits

  • SambaNova vs Rubin

  • SambaNova vs Groq vs Cerebras

• Where does this leave SambaNova

Disclosure: This is not a sponsored post. SambaNova provided their inputs on a draft version of this post, primarily on their use cases and nomenclature which has been incorporated into the post. Opinions are my own.

If you are interested in other inference hardware deep-dives on this newsletter, check these out:

If you are not a paid subscriber, you can purchase just this article using the button below. You can find the whole catalog of articles for purchase at this link.

Buy the ebook

The Three-Tier Memory Architecture

Let’s say you have a bunch of small models tuned to do one thing really well. Each “expert” could be a coding model, a writing model, a sales model, and so on. To quickly switch between these experts, each expert’s weights need to be stored in high-capacity memory (like DDR) that can be quickly swapped into a faster memory tier (like HBM) with latencies in the microsecond range, and the hottest weights loaded into SRAM. This is what SambaNova’s 3-tier memory architecture is built to do; all tiers are addressable directly from the chip, each with their specific function.

• Per model layer scratchpad: On-chip SRAM (several hundred MB per chip)

• Working model weights: CoWoS-attached HBM (several tens of GBs per chip)

• Cold storage of model weights: DRAM (1 to 2 TB) on the board level per socket.

Loading these weights from network storage over InfiniBand is too slow for frequent back-and-forth trips between different expert models serving different tasks. The three-tier hierarchy gives you a lot of memory and keeps all of it close enough to compute to be useful during inference. SambaNova is not the only startup to envision multiple memory tiers for inference. MatX, for example, uses a mix of SRAM and HBM. d-Matrix uses a combination of SRAM and 3D DRAM. All of them have different approaches to solving the memory bandwidth problem.

The table below shows the specifications of different memory tiers in SambaNova’s last two chip generations: SN40L and SN50. A key point to note is that the SN50 actually went back a generation in HBM: from 3 to 2E. Edit: SambaNova pointed out that both SN40L and SN50 are on HBM2E while also being on TSMC 5nm; the table below reflects that. But, there is an actual architectural reason why HBM bandwidth does not always matter for SambaNova. We’ll get to this later.

To really understand how this memory architecture works with either model bundling or true MoE models, we need to understand how RDUs work first at the chip level, and then at rack scale. This really matters for how data flows through the system.

Understanding How RDUs Work

A reconfigurable data unit or RDU is just two primitives that are repeated many times on the chip, and wired together with a programmable switch fabric. The two primitives are:

• Pattern Compute Units (PCUs): These are the arithmetic engines. Each PCU can perform multiply-accumulate operations, perform softmax operations for attention calculation, or layernorm operations. The compiler decides ahead of time what the PCU does, and what flows in and out. SN40L has 1,040 PCUs per socket (across two dies); SN50 has roughly 2,080 PCUs per socket (across two chiplets).

• Pattern Memory Units (PMUs): These are the on-chip SRAM scratchpads. PMUs hold the weights and activations that feed the surrounding PCUs. The 520 MiB of on-chip SRAM on SN40L is spread across 1,040 different PMUs. Same arrangement on SN50 (432 MB across ~2,080 PMUs). Each PMU sits physically next to the PCUs that read from it, so the bandwidth between scratchpad and compute is local and short.

The switch fabric is a programmable interconnect that wires PCUs and PMUs together. The compiler determines what data moves from one PCU to another over the fabric at any given time.

To show how the RDUs sharply differ from a general purpose GPU, we must understand how computations are done on both, and where the RDU shines.

Here is how the process of inference works in a GPU. Each operation (or kernel) in the process of inference is written to HBM and then read back for the next step in the calculation. The figure below shows this in more detail. First, RMSNorm is calculated and the result is sent to HBM. Then, all the info along with weights is read back for QKV calculation and so on. The problem with this approach is that there are a lot of memory accesses along the way which increases latency, and burns more power shuffling bits in and out of memory.

Here is how SambaNova does it: They assign all the PCUs and PMUs on the chip to various parts of the inference process. As shown in the image below, you can literally gerrymander your way through memory and compute cores via the software compiler. The computations are done on the PCUs, and the intermediate weights and results are stored in the PMUs. In a sense, the SambaNova compiler predetermines the “dataflow” across the chip – that is, how to split up the available data units to perform different functions required for inference.

By keeping the entire calculation process on the chip, the data never leaves the chip to external HBM memory. HBM is only present to load up the weights into PMUs, and is not really used in the computation process. This explains why SambaNova can get away without using the latest HBM4 or HBM4e because their architecture simply does not demand extreme memory bandwidth from HBM. All relevant data for inference stays on the chip, and when something more is needed, it is read from HBM. They can however, still benefit from HBM4, as we will see later.

Scaling up to the Rack Level

Now this is just one chip, and you might be thinking that a few 100 MBs of SRAM is not going to cut it. The real picture starts coming together when you look at it at scale. Each “SambaChassis” (my name for it, not SambaNova’s) has 8 RDU chips, and two x86 CPUs – likely Intel Xeon 6s, from the looks of it, based on recent partnership announcements. You can put 2 chassis per rack, for a total of 16 RDU chips.

This entire rack acts as one giant chip, and you can basically break up the process of inference across all of them in any slice-and-dice way you want because they are all on the scale-up fabric. You can route your datapath through any of the RDUs across the entire rack.

Across a rack, you get ~7GB of SRAM and 1TB of HBM. Arguably, this is significantly less than Cerebras WSE’s 44GB per wafer, and you get two WSE per rack, which is 88GB of SRAM per rack. Also, 1TB of HBM is on the low-side on rack scale because just 4 Rubin chips will get you the same 1TB of HBM. A Rubin NVL144 (with 144 GPU chiplets) has 20.7TB of HBM in a single rack. We will make more detailed comparisons after the paywall.

Future SambaNova chips would surely benefit from the use of HBM4 instead of HBM2E, but the short supply and pricing is always a concern for smaller players.

You can also run different kinds of parallelism: tensor, pipeline, or expert, on the entire rack of 16 chips. When you scale up to multiple racks, the ability to slice up the data units across all 256 RDU chips makes it quite versatile as to how you can split up a large model into various pieces of hardware in the system. SambaNova’s video below explains a lot of this quite well:

Where SambaNova Fits

In terms of a deterministic compiler and SRAM capacity, SambaNova resembles Groq more than Cerebras or Rubin, but with one major difference: the ability to shape the performance based on the workload due to availability of both HBM and DDR memory tiers. This allows KV cache storage within the memory hierarchy without the immediate need for external appliances. Unlike Groq which is a one-trick pony, and Cerebras which suffers when handling large models, SambaNova is a swiss army knife due to compiler driven scheduling and high capacity memory tiers.

After the paywall, we discuss:

• How SambaNova compares to Rubin

• How SambaNova compares to low-latency inference hardware like Groq LPU and Cerebras WSE

• The real benefits of SambaNova: 3-tier memory hierarchy, RDU’s versatility, and TCO

Read more

Here’s a recap of content this week:

• 📖 Cerebras IPO and the Four Bottlenecks in Its Custom-Everything Architecture

• 🎙️Power as the next physics wall for AI

• 🎙️Gimlet’s cross-vendor inference cloud

As part of the Semi Doped ecosystem, we also have a daily newsletter where we post our takes on industry news in the semi space . We are now 1,000+ subscribers strong. So if you haven’t signed up for that, get in on it now.

Semi Doped

Semis and AI commentary from Vik Sekar and Austin Lyons

I want to use this TWiC format going forward to explore undeveloped themes that I am thinking about that will eventually convert into deep dives on this newsletter. Let me know what you think.

GaN or SiC for Power Devices?

There is a question among investors about whether gallium nitride (GaN) or silicon carbide (SiC) is better for power devices, particularly as the industry pushes toward megawatt-scale racks and an impending power wall in AI data centers.

At the fundamental physics level, it does not matter. Both are wide band gap devices, which is a technical way of saying that transistors built from these materials can handle a lot of power before they break down. Depending on the voltage level the transistor can handle, both transistors can be used in power converter applications.

Broadly classifying transistors by material they use is reductive. Take GaN for example: it really depends whether we are talking about GaN-on-Si, GaN-on-GaN, or even vertical GaN. All these affect the voltage handling, and switching speed of these devices (how fast you can turn them on or off).

A lot also depends on which stage of the conversion process you are talking about; closer to the GPU or closer to the grid. A lot of things matter here. We’ll explore all this in a future deep dive. But at the surface level, just know that it's not like one is automatically better than the other.

Why is everyone talking about Wolfspeed?

Remember that this was a company that was in the brink of death just a few months ago. You can check their stock price: it hit $0.5 at some point in the recent past. And, now it’s at about $70. So what’s going on here?

Wolfspeed basically overbuilt SiC manufacturing for EVs and when demand took a downturn, primarily due to massive capacity from China, they were left holding the bags. They even filed Chapter 11 bankruptcy. Mind you, the company is still running at a GAAP net loss of $120M according to recent earnings.

The recent interest in the company, I think, is coming from this one SiC transistor that no one else has. Picture shown below.

This is SiC MOSFET that holds off 10kV of voltage, which is something that only SiC can really do (not sure if GaN can; I haven’t looked). The other alternatives are 6.5kV Insulated Gate Bipolar Transistors (IGBTs) which are silicon based. SiC also switches at a higher speed compared to IGBTs which allows the use of smaller magnetic components in power conversion.

So why is this component so important? You see Medium Voltage (MV) transformers are in very short supply, with backlogs going back 3 years. See this Reuters article, from where I took the screenshot below. This is becoming a serious problem for datacenter buildouts.

What power SiC does here is replace these power transformers that use an iron core and windings with SiC based voltage converters that operate by switching the transistors on and off. This makes for a very interesting use case that deserves looking into. Also, read talk about this. The whole interview is great. also wrote a memo about power semis that really kicked up WOLF stock a notch.

If you’re interested, read this whitepaper from Wolfspeed. We’ll break the tech down in a much simpler fashion in a future deep-dive with wider context.

Semtech CopperEdge

This one is another Irrational Analysis pick from the interview link above, and I’ve had a few people ask me about it. Really haven’t gotten deep into it, but at the surface, it seems like Semtech is a company that was typically known for some IoT and LoRa (long range) stuff that few really care about these days. As it turns out they have a bunch of people who really know how to do analog semis and design some equalizers/redrivers for copper interconnects — the real magicians of semis.

Note that cables when used with Semtech chips will not have DSPs — which puts them more in the class of Active Copper Cables (ACCs) rather than Active Electrical Cables (AECs). I have a post on this from a while ago, if you want to understand it better.

This is crazy to me, because at 200G/lane, I’d imagine you’d need DSPs and pay the power-price for this stuff to actually work. But no DSP? That means straight up power savings — I need to understand this analog magic better. In simple terms, their approach goes something like this:

• The degraded analog PAM4 signal comes in.

• The chip selectively boosts the weakened high-frequency components (while keeping the overall waveform linear/transparent).

• It outputs an amplified, equalized analog signal that the receiver can still understand.

• No ADC, no DSP core, no DAC, no re-clocking.

This means, each cable end is <2W or ~1.25 pJ/bit at 1.6T. Most AECs like Credo HiWire are closer to the 20W range per cable end or 12.5 pJ/bit. I am not sure what the power efficiency of Marvell Alaska AECs at 1.6T is, but even if its 2X better than Credo, or 10W per cable end, it’s still 5X worse than what Semtech is saying they can do.

No DSP also means near real time analog latency that is in the 10s of picoseconds (versus nanoseconds with DSPs). This is meaningfully important for the scale up domain where latency matters a lot, in addition to low power.

I’ve got to look into this stuff in a deep dive. Just some off the cuff reaction thoughts when I looked up this thing, and is not an endorsement for the company.

I clearly have lots of work to do here. Let me know how you like the “unfinished thoughts” approach to this edition. Oh, and have a great weekend!

What this is not, in my read, is a technology displacement story. Nvidia and Groq LPUs serve the low-latency segment of inference, and can hold its place in the overall inference market. It’s not always zero-sum as the market likes to think it is. Cerebras on the other hand, has massive customer concentration risk in G42, has compute (not hardware) purchase agreements with OpenAI, and lacks the overall software and hardware ecosystem that Nvidia has for its LPUs from Groq.

The investor question is not “does Cerebras affect Nvidia,” but whether the custom-everything architecture can scale revenue past strategic deals with OpenAI without breaking on a single design choice or supplier. We’ll work through four risk vectors in this piece.

If you are not a paid subscriber, you can purchase just this article using the button below. You can find the whole catalog of articles for purchase at this link.

Buy the ebook

How Wafer-Scale Inference Actually Works

The central idea to Cerebras’ silicon is the Wafer Scale Engine (WSE). While GPUs/TPUs are often diced out of a whole 300mm wafer and then packaged, Cerebras keeps the whole wafer intact – the wafer is the chip and it is 46,225 mm2 in size. The latest iteration WSE-3 has 900k processing cores, 44GB of SRAM per wafer, and a memory bandwidth of 21 PB/s per wafer. For comparison, Groq LPUs “only” have low 100s of TB/s per chip.

To be clear, Cerebras built this enormous wafer-scale chip for training so that the model can remain on the wafer to speed up GPU cluster training by skipping the slow network links between GPUs. But this idea never caught on for training for a couple of reasons:

1. Memory bandwidth was never the constraint for training.

2. CUDA was entrenched in the training phase, and there were no incentives for AI labs to break convention and risk falling behind.

But the arrival of disaggregated inference (prefill+decode, attention+ffn) presented a new opportunity. While the prefill stage was mostly compute bound, the decode stage is entirely memory bound. SRAM is the highest bandwidth memory tier possible, and what better way to get as much of it as possible than to make a chip the size of the wafer. If you want a deeper look at SRAM for inference, see this earlier post.

The end result is that the decode phase of inference is sped up enormously due to the WSE’s memory bandwidth. Since large models require more than the 44GB of SRAM available per wafer, a trillion-parameter model will require multiple WSEs to hold the weights and KV-cache. Since only activations flow between different WSEs, the need for high speed interconnects between wafers is not as much. Various forms of parallelism – model, tensor, pipeline – can be implemented between the different WSEs to implement a full scale model.

While the technology is certainly cool, this level of inference performance is not always necessary. In February this year, OpenAI was reportedly looking to replace 10% of its inference compute with low-latency hardware. The ultra-fast decode only makes sense in a few applications that require real-time performance, or where faster inference literally means money. For most of the inference market, GPU-based inference is the right answer. So like all low-latency inference hardware, this is not a “GPU/xPU killer.”

Yield, Stitching, and the TSMC Lock-In

Wafer scale chips are not a new idea. In the 1980s, Trilogy Systems led by Gene Amdahl famously tried it and failed, concluding that wafer yields need to reach extraordinary levels for this idea to work. The Chip Letter on Substack has a nice series of posts on the history of wafer scale chips (Part 1, Part 2).

Cerebras made it work with a combination of clever engineering that reroutes around to processing units that have defects, to spares on the chip. There are 900k working cores, but closer to a million physical cores on the wafer that are configured at the software level to appear “defect-free.” Cerebras has spent close to a decade with TSMC working out the redundancy schemes, the wafer-level interconnect, and the packaging that makes the WSE physically viable, none of which a competitor can replicate easily. Cerebras has solved wafer-scale chips. You can read all about it here.

The key point to note here is that the foundry lock-in with TSMC for Cerebras is real. The entire process of stitching multiple reticles together to create a wafer-scale chip is not something that easily translates to another fab that may have better capacity for scale.

The OpenAI Deal: Cloud Service, Not Hardware Sale

The agreement with OpenAI announced January 14, 2026 works like this. 750 MW of compute capacity will be deployed over 3 years, with an option for OpenAI to expand to 2GW total through 2030. The S-1 values the base 750 MW commitment at more than $20 billion.

But OpenAI is not buying hardware. Cerebras is building or leasing the data centers, filling them with WSE-3 systems, and operating them as a cloud service. Several people I’ve spoken to have said that running your own token factory with your own hardware is not where an inference hardware provider wants to be. They’re forced to do so only if people are not buying their hardware directly. Remember that Groq was pushed into selling tokens via GroqCloud as well, until Nvidia came in and paid an extraordinary amount of money to acqui-hire them.

So in reality, OpenAI pays Cerebras for compute time, not for equipment. Cerebras keeps the infrastructure on its balance sheet, recognizes recurring service revenue, and is operationally on the hook for running AI data centers at scale. The financial structure has a bit more detail worth looking at:

1. OpenAI advanced Cerebras a $1 billion working capital loan at 6% interest, with the interest waived if the loan is repaid through capacity delivery rather than cash. This is effectively prepayment for compute dressed up as a loan, and it funds Cerebras’ upfront capex for building out systems.

2. Cerebras issued OpenAI a warrant covering ~33M non-voting shares at a near-zero strike price ($0.00001, ok basically free), vesting as OpenAI actually purchases capacity, with full vesting only on the full 2 GW deployment.

As it stands today, Cerebras’ fortunes are tied to OpenAI’s success, and their own ability to deploy and operate at large-scale, which is something they have never done before. Their other source of revenue comes from direct hardware sales to G42 and MBZUAI (in the UAE), and represented a disproportionate share of 2025 revenue (86%). But revenue from running cloud based hardware is expected to be the real growth vector for the future.

The architecture, the deal, and the moat are the publicly debated parts of the Cerebras story. The four risk vectors after the paywall are less discussed and matter more to what puts Cerebras’ ability to scale, in danger.

Read more

Here’s what you might have missed this week:

This article has been very popular because there are good reasons why nature pushes us up against a wall when it comes to power delivery. Give it a read; lots of tech content even before paywall.

Memory is just stupid expensive, but Deepseek V4’s SSD focus has implications for NAND. More on the Semi Doped Podcast.

Finally, if you want to keep up with daily news updates fresh and hot off the press, sign up for free to the Semi Doped Substack. Austin and I both post our takes there; easy and quick to read with your morning coffee. ☕

Semi Doped

Semis and AI commentary from Vik Sekar and Austin Lyons

Now, on to the news.

GlobalFoundries SCALE vs TSMC COUPE

GlobalFoundries’ SCALE (Silicon photonics Co-packaged Advanced Light Engine) is an optical module solution for co-packaged optics deployment in AI data centers, while being compatible with Optical Compute Interconnect Multi-Source Agreement (OCI MSA).

TSMC is the king of CPO today and COUPE goes to mass production this year with NVIDIA, Broadcom, and Ayer Labs as customers. But TSMC integrates the EIC and PIC on SoIC-X with hybrid bonding under one roof, and ties the whole stack into CoWoS. GF makes the PIC, but the EIC has to come from a different fab on a “single-digit advanced node,” which means TSMC or Samsung.

The new piece is the OCI MSA badge: Hyperscalers want optionality. The interesting angle is that OCI MSA changes the structural opportunity. If hyperscalers force multi-source qualification for scale-up CPO (the explicit goal of the MSA), GF’s TAM expands because customers are required to qualify a second supply chain. The bigger winner in this story isn’t GF. It’s the hyperscalers, who have the option to move scale-up optics from a proprietary fight to an open spec.

(via GlobalFoundries)

Apple, Intel Have Reached Preliminary Chip-Making Agreement

Very big news for Intel, and stock is up a lot . While still not clear what product line from Apple will be manufactured at Intel, TSMC’s underinvestment in chip capacity is systematically giving away the keys to the kingdom to its competitors. For Intel, this is a much needed big customer for its Foundry services. This deal also brings back chip manufacturing back into American soil, possibly in a large way, depending on the order volumes Apple places with Intel. Intel has been killing it recently with CPUs, advanced packaging capacity via EMIB (another TSMC kingdom key), and now Apple business. Can’t stop winning.

(via WSJ)

Nvidia Invests $2.1B in IREN for AI Infrastructure

Nvidia announced a strategic partnership with infrastructure provider IREN, investing up to $2.1 billion to accelerate large-scale deployment of AI data center infrastructure. The partnership targets building up to 5 gigawatts of AI infrastructure capacity, combining Nvidia’s computing platforms and GPU accelerators with IREN’s infrastructure development, deployment and operational expertise.

This is now the standard NVIDIA neocloud financing playbook. NVIDIA stitches together a GPU buyer’s capital stack by:

• Selling them GPUs (revenue)

• Becoming an anchor tenant (revenue for the cloud, recycled back to NVIDIA)

• Taking equity exposure to participate in upside

The capital stack of every major neocloud now includes NVIDIA either as direct equity, warrants, anchor customer, or all three. That concentrates systemic risk, but it also means NVIDIA can keep volume flowing even when traditional financing tightens.

(via Nvidia News)

Optics Industry Update

Biggest optics names reported this week: . All either beat or printed strong growth. All four sold off.

Main thing happening here: When everything is up 1,000%+ YoY, anything short of perfection becomes a sell signal. Hurlston during the LITE call: “We are significantly undershipping demand. And we’re having to make choices as to who we support.” Usually that’s bullish but now it tells investors you are capacity-bound, which means upside is now governed by how fast you can add capacity, not how fast demand is growing.

Also keep a close watch on microLEDs and VCSELs for short reach interconnects. More companies are optimizing microLEDs for datacenter applications, and not inheriting tech from display industry. Longer wavelength VCSELs at 980nm and 1060nm have distinct benefits at 200G/lane (needs a deep dive - interesting physics). ams OSRAM making moves into AI interconnects as well.

Optics is still important but a lot of the big names are priced in already. While they should still grow, just don’t expect 1,000%+ returns again.

Evercore ISI: Cisco Silicon One is Underrated

Silicon One is Cisco’s family of networking chips. It started in 2019 inside Cisco’s own routers, and over time Cisco opened it up to sell directly to hyperscalers as merchant silicon. The latest parts are the G200, a 51.2T switch chip, and the P200, a deep-buffer router chip. Microsoft and Meta are the named hyperscaler wins. For most of its life, Silicon One has been a small line item buried inside Cisco’s revenue base, and the buy-side has indexed Cisco as a slow-growth networking vendor rather than an AI silicon play.

This week, Evercore put a number on it. Silicon One could ramp from ~$3B in FY26 to $12-15B in three to four years, with roughly $7-8B in silicon and $5-7B in attached optics. The silicon number would put Cisco at roughly Marvell-scale and credibly third behind Broadcom in merchant networking ASICs.

Have a great weekend!

Power density in a datacenter is an important metric for two reasons:

1. Land usage: There are geographical, environmental, social, and economic limitations to how big a datacenter campus can be. Beyond that limit, multi-datacenter campuses become necessary which complicates infrastructure.

2. Networking complexity: It is better to put as much compute in a single rack as possible so that networks span short physical distances, for which copper will suffice. Spanning different racks, buildings, or campuses increases power cost due to the need for optics at different levels, or active electronics for copper interconnects.

In an earlier article, we covered why datacenters need to shift to 800V DC in quite some depth, including an in-depth discussion of electrical systems in datacenter campuses.

What may not be obvious is that deploying high voltage datacenters is not as simple as retrofitting existing buildouts; true high voltage infrastructure needs greenfield buildouts. This is why early implementations of HVDC architectures by OCP Mt. Diablo and Nvidia’s Kyber rack have DC sidecar racks that handle 800V power supplies instead of natively routing it through the datacenter.

The essence of power delivery to a datacenter relies on keeping voltages as high as possible, for as long as possible, before it is delivered to a GPU. There are good physics reasons for this, which we will cover.

The question of how to generate power, where to convert the voltage, what kinds of devices are needed to do so, what is the most efficient method, and what is the most scalable approach as power in datacenters continuously increases, is where the whole discussion lies.

Several notable analysts are pointing out that power delivery is becoming increasingly important. Recently Wood Mackenzie reported that there is a structural shift in the demand for electrification, and a string of shortages in the supply chain. ON Semi CEO stated that power semi content will be 10x with the move to 800V DC racks, with additional semi content in power conversion outside the rack. Notable analysts like SemiAnalysis and Citrini Research are also pointing out that the “power plumbing” of AI datacenters, while seemingly boring, is showing a real inflection point in demand.

In this post, we will map out the landscape of power semiconductors. We will not cover power generation, industrial hardware, and delivery systems at the grid level here, or even outside the rack; that is a different discussion. We will look at the physics reasons for higher voltages, voltage conversions within the rack, and the engineering trade-offs in doing so. Finally, we will identify which architecture wins in the near and longer terms.

We will cover:

• Power physics that forces the rethink

• Power conversion architectures

• Which 800V architecture wins

If you are not a paid subscriber, you can purchase just this article using the button below. You can find the whole catalog of articles for purchase at this link.

Buy the ebook

Power Physics that Forces the Rethink

It’s instructive to draw parallels between power and interconnects.

The reason optics is becoming increasingly popular is because skin-effect in copper wires increases its resistance. This is an effect that occurs when alternating currents flowing through a wire only utilize the periphery and not the entire cross section of the metal wire. This gets progressively worse as the speed of the signal increases. Optics is immune to this effect because light propagates through glass fibers; electrons and metals are not involved.

The consequences of interconnect physics in copper and optics is that you want to stay in the optical domain as long as possible, and convert to electrons as close to the chip as possible – this is the fundamental idea behind co-packaged optics, or CPO.

Now let’s turn to power.

When electrical signals flow through grid transmission lines, they have losses due to skin effect too. But this can be mitigated by using high voltage lines often in the 100 kV range for power transmission. This ensures that the currents flowing are low in magnitude, thereby resulting in lower losses. The power is converted to medium voltage (10-30 kV) only at the substation in a datacenter, and distributed at 400-480V 3-phase AC within the datacenter halls. AC is converted to DC at the rack level to 48V by the power supply units (PSUs), then down to 12V by intermediate bus converters (IBCs), and finally down to 0.8V-1V by voltage regulator modules (VRMs).

The rack scale voltage of 48V is important. To deliver P=600 kW (rating of the Kyber rack used to house the Rubin Ultra) at V=48V requires I=12,500A of current (P=VI). This level of current has serious implications.

1. Resistance headroom: If only 1% of the voltage budget (1% of 48V = 0.48V) should be lost to power delivery, then the total resistance from the rack PSU to load should be 0.48V/12,500A = 38 micro-ohms (R=V/I). This covers the busbar, joints, connectors combined, leaving no headroom; that resistance is already very low.

2. Copper weight: Busbars are thick metal buses that carry current, and practically supports about 1,000A/sq. in, before heating becomes a problem. For 12,500A, the cross-section of copper needs to be 12 sq. in (say 4” x 3”) that runs a full rack height of 7’. This puts the copper busbar volume at ~1,000 cubic inches per rack. Assuming copper density of 147 g/cu. in, each busbar then weighs 147 kg/rack. The cost and weight of this much copper is unmanageable.

3. Power dissipation: The power dissipated by this much current is I²R, which means that a linear increase in current results in quadratic power losses. With 12,500A of current and 38 micro-ohms of resistance, the power dissipated is 6 kW, which requires significant cooling efforts.

One way to greatly mitigate all these problems is to move to higher DC voltages like 800V.

At this voltage, 600 kW of power needs only 750A of current in the rack. 1% voltage budget leaves 8V/750A ~ 11 milli-ohms, which is much better headroom than micro-ohms. Copper busbars can be 1” x 1” and still support up to 1,000A. Busbar volume drops to 84 cu in, or 12.3 kg/rack which is much more manageable. Power dissipation assuming 1 milli-ohm resistance (25x worse than 38 micro-ohm case) is 0.56kW, which is much 1/10th of the 48V case, and better to handle cooling-wise.

All these numbers show one important implication: use high voltages as long as possible, before converting to lower voltages near the chip.

Just like optics has CPO, the equivalent in power delivery is called “Point-of-Load” (PoL), where only specific implementation is called Vertical Power Delivery (VPD). The main idea is to convert the high voltage to low voltage, right under the GPU where it is actually used.

How exactly voltage is converted from the 48V or 800V down to 0.8V required by GPUs is where all the engineering lies, and is what defines the entire competitive space of power semiconductors in AI datacenters at the rack level. Now that we have established why higher voltages are necessary, the next question is how to step down efficiently from 800V or 48V to the GPU core voltage.

Power Conversion Architectures

The power conversion architectures at 48V and 800V are shown below. These do not cover every possibility, but are sufficient to understand the trade-offs in each case. For each architecture, the number of conversion stages and voltage choices at each stage determine the overall efficiency, cost, and dynamic behavior of the power conversion. The 12V or 5-6V stages in blue are often called Intermediate Bus (IB) voltages. We will discuss these trade-offs at a high level.

Number of conversion stages

Every stage of power conversion has some power loss, and hence fewer conversion stages means lower loss, to the first order. Even a 97% conversion at each stage results in a 91% overall efficiency for a 3-stage power convertor. The per-stage conversion efficiency depends on the actual voltage values at the input and output, and efficiency of each stage need not be the same. This is overall a simple concept: fewer stages, lower loss, higher efficiency. So why not just convert all voltages in a single stage?

Voltage Levels and Conversion Ratio

Every stage of voltage conversion typically uses a completely different kind of converter, which implies that there are different companies that capture varying amounts of value depending on the power conversion architecture being deployed. The output to input voltage ratio and the actual voltage values drive circuit topology choice.

Three constraints determine the voltage levels and the topology choice at each stage: isolation requirements, conversion ratio efficiency, and the need for tight voltage regulation at the final stage.

1) Isolation and the SELV threshold

SELV stands for Safety Extra-Low Voltage. The IEC 61140 standard defines a SELV circuit as one where the voltage between any two conductors, or between any conductor and earth, does not exceed 60V DC (often used in practice even if spec is higher) under normal and single-fault conditions. Below this threshold, current through a person making direct contact is unlikely to be fatal. Above it, the circuit must be galvanically isolated from any electrical conductor a human can touch, which usually means a transformer separating the primary and secondary sides of the converter (these are magnetically coupled, and have no wires from input to output, which isolates them galvanically).

This is why 48V and 54V rack voltages exist where they do because they sit just below the SELV ceiling. Anything downstream of the 48V busbar can be non-isolated, which removes the transformer from the converter and saves space, cost, and a percentage point or two of efficiency.

For architecture, the rule is simple. Any conversion stage with input above 60V DC needs an isolated topology. AC line to 48V is isolated. 800V to 48V is isolated. Once at 48V or below, no further isolation is needed, and the rest of the chain runs on non-isolated converters.

Beyond isolation, two more constraints determine which converter sits at each stage and which vendors compete for that socket. These constraints, and how they map to the 800V architectures, are where the investment thesis lives.

Read more

Without much ado, here’s my “big update.” After 15 years of working in professional semiconductor companies, I’ve decided to strike out on my own. My focus will be around researching and writing about semiconductors on Substack, building out the Semi Doped podcast, and expanding into consulting. That’s the grand plan at least.

Why the big change?

Having worked at small, medium, and large companies, I’ve realized that there is so much more to the world of semiconductors than I’m privy to, compared to my daily duties on the job. I started this newsletter in 2024 to explore my curiosity and find out what else is out there; to give myself an opportunity to learn and explore technology on my own, without concern for whether it results in career advancement.

Even with many years of work experience, I realized how little I knew about how the industry works. Every piece of technology has vast technical depth and nuances that are humbling, and many times I only scrape the surface of what lies beneath. Staring into the abyss of the unknown excites me more than it intimidates me. Today, my content channels are merely a way for me to explore that technological abyss and see what lurks beneath the surface.

I often relate to my PhD years as my best years but I never stopped to question why. Most people speak of it in tortured terms, but I’ve always looked back fondly at it. I did well too, by any conventional metric. I graduated with well over a dozen journal and conference papers to my name, including an award at an international IEEE conference. This, I naively mistook for intelligence - as if, somehow writing more papers makes me smarter. My fresh academic brain knew no better.

For a while, I considered getting into academia. I even applied to universities. My wife maintains to this day that I am an excellent teacher; I did the impossible by teaching her mathematics for her GRE. But I had seen the seedy underbelly of university life in my PhD years and it wasn’t something I was eager to jump into. Industry was the obvious alternative for someone with an engineering degree like me. I entered the workforce in 2011 and it was not the best of times (perhaps it was the worst - for some). I had applied to 77 jobs, got 3 callbacks, and 2 offers. I picked the job in California since the pay was more. The “spray and pray” approach worked for me luckily.

Ever since then, I have genuinely had a lot of fun in the industry for well over a decade, and have met a lot of smart people along the way. At some point, it became clear to me that it was always going to be the “same thing, different place.” Nobody tells you how hard it is to change course once you have experience in a certain thing. You’re stuck doing the same thing forever, even if you don’t like it anymore, because you’re the expert now. Some people do however change roles with chameleon-like versatility. I never figured out how.

I was lucky in a sense. My best professional years were dead centered around the wireless explosion. My skills were perfectly aligned for the 2010s even though everyone told me a decade before that doing electromagnetics for a living was a poor professional choice. When I joined my last employer, 5G was a matter of national concern. In the last 3 years however, the semiconductor industry has been … different.

The birth of transformers has led a semiconductor renaissance that I never imagined I would see in my lifetime. The last time semiconductors were this sexy were in the 1970s, when Robert Dennard taught us how to scale transistors. In the modern era, my skills started to seem dated, from a time gone by. I have started to believe that wireless technology is largely a solved problem today. The world of artificial intelligence however, appears ripe with opportunity. The highest agency action I could undertake was to just learn everything about it I could. Not for a job change, not to convince someone, but for the sole reason that it was cool.

Substack was the perfect motivator. I had to learn something new to write every week - a cadence that I have largely kept up since the birth of my Substack in Jan 2024. As I kept churning out articles, it struck me. The reason I enjoyed my PhD was because I expressed complicated technical knowledge in simple words. My language in papers was not particularly stuffy, and my guess is that reviewers found my papers easy to read. Nearly every paper I wrote was accepted with minimal objections. Perhaps complex technical ideas, curiosity, and language were my Ikigai somehow. An odd combination, but it only makes sense in hindsight.

Today, I work more than I ever have. But it comes from a place of happiness - of doing what I truly enjoy. Through my writing, I have made so many connections with people that were never possible before. The commonly touted mantra of “writing makes your life better” is actually true. I recommend everyone to try some form of it.

With the support of all my paid subscribers, the newsletter income has grown to a point where I can support my lifestyle by writing on Substack – to where I can say I have “enough” to continue doing this full-time and hopefully have a lot of fun along the way. Thank you to everyone who supports this publication.

It’s all about figuring out one thing at a time. I have location and time freedom to a large extent now – which I fully appreciate. Being my own boss is liberating, but also scary. You stop working, you stop getting paid. I am also hoping that the Substack will continue to grow.

The Semi Doped podcast with Austin Lyons has been a fun endeavor, and we plan to grow out this channel with sponsorships and such. The newly-minted Semi Doped substack is an extension of the podcast – quick hits on the semi industry, without the depth. We want to grow it to be the Morning Brew, or 1440, of semis. Free to read, but sponsor driven. Reach out to us if you’re interested in sponsoring the Semi Doped newsletter or podcast.

Finally, I’m slowly building out SemiExponent – the consulting arm of my semiconductor work as well. If you would like to work with me, feel free to reach out to me at vik (at) semiexponent (dot) com.

Regular programming for ViksNewsletter will resume next week. Paid subscriptions have been paused, but you can still sign up for the free tier. Everything will resume as normal from April 30th.

Till then, I’m off to the beach!

I am pausing subscriptions for just under a week (April 25th - April 30th) since I am leaving for a week’s vacation today. Your existing subscription will extend accordingly, and you will still have access to all paid articles. New paid subscribers cannot sign up in that time. There will be no deep-dive and TWiC next week, but there may be a Semi Doped podcast from the beach. 🌊 Not sure yet.

Substack deep-dive this past week was about a new optical pluggable format called XPO spearheaded by Arista Networks, and how that matters for CPO.

CPUs for agentic AI are becoming hotter, and demand far outstrips supply at the moment. In light of this, I have removed paywalls from my most widely read, and highest revenue generating post ever on this Substack, so more people may have access and get a sample of what kind of content lies behind paywalled deep dives.

I wrote about this just about two months ago, when other sharp analysts like were calling out CPU shortages. The deep dive outlines why agentic AI demands more CPUs. Also, the post has been updated to add comparisons to ARM AGI CPU as well.

On the Semi Doped podcast, we spoke about Credo acquiring Dust Photonics, more XPO discussions, and a new AI CPU company - NuvaCore.

We’re also starting up a Substack presence for Semi Doped where Austin and I will write our commentary on industry goings on as a complement to the podcast. Our intentions are to keep this entirely free, less crazy technical, and accessible to a wide range of people interested in keeping a pulse on the semiconductor industry. It’s meant to be easy reading. Do sign up and tell your colleagues!

Semi Doped

Semis and AI commentary from Vik Sekar and Austin Lyons

With all that housekeeping out of the way, let’s get to the news.

Google announces TPU v8 chips and new networking architectures

Google Cloud Next is the biggest piece of news this week where the company announced their newest line of TPU chips: v8t for training and v8i for inference. This is the first TPU generation where there are two SKUs with different chip specifications. It is now clear that training and inference have different hardware needs: in both chips and networking.

Few interesting things to note:

• HBM capacity on the inference chip is higher than training. Memory bandwidth is critical for inference performance as more people and agents use AI. Training is not really general public facing, and you can build out a datacenter with more GPUs even if lesser HBM exists. It’s still not clear to me why not max out everything.

• Look at the on chip SRAM on TPU 8i! It’s 3x higher than the training chip. Having SRAM allows you to automatically provide fast inference without having to use special chips like Groq LPU. The TPU 8i with its SRAM bandwidth can actually decode really fast. I’ve always maintained that having SRAM is the key here, not strange architectures like Groq’s VLIW architecture. In any case, Google TPU’s systolic arrays do provide deterministic behavior like Groq VLIW.

• Arm Axion CPUs as the head node. This is a chip developed internally by Google based on Arm architecture. More evidence that ISA is not really that important anymore.

Finally, the networking innovations.

• At the scale-out level, Google’s new Virgo architecture replaces their Jupiter network by using Optical Circuit Switches (OCS) with high switch radix. This allows a lot of chips to be connect with just two networking layers, greatly reducing latency.

• At the scale-up level, the training chips still use 3D torus. The interference chip networking now goes to a Boardfly approach.

  • 4 TPU 8i chips to a board — connected by copper

  • 8 boards to a rack (also called group) — connected by AEC

  • 36 groups to the pod — connected by OCS

  • Total 1,152 TPUs per pod

The underlying substrate for all of Google’s TPU networking is OCS. This is a structural change that makes future Google datacenters heavily rely on both optics and copper. I explain the entire networking aspect in-depth on Semi Doped. Look out for the next episode on YouTube.

Intel goes from surviving to thriving

Just a year ago Intel was struggling for existence. TSMC was about to get control of Intel Fabs and help resurrect the business - a brainchild idea of not-quite-loved ex-chairman of the board Frank Yeary. Even Qualcomm allegedly approached Intel for a takeover.

In a riches-to-rags-to-riches story - a comeback story that everybody loves - Intel is now in a position of dominance across three different assets: (1) x86 CPU franchise, (2) advanced packaging, and (3) their massive chip manufacturing network.

The rise of CPUs for agentic AI is a gift that fell in Intel’s lap because it precisely aligns with their core competence. It is up to execution at this point. TSMC’s CoWoS is so bottlenecked that Intel’s EMIB packaging is getting increasingly higher order backlogs. Seemingly, their 18A yields are improving as well. The AI story is playing out because, according to Intel’s latest earnings call, their AI-driven business represents 60% of revenue and grew 40% YoY.

It’s not just CPUs though. Lip-Bu stated on the earnings call that they are “quietly building up the GPU with a new hire” — which refers to Eric Demers being hired as Chief GPU architect earlier this year, who also led Qualcomm’s GPU efforts before he joined Intel.

Lip-Bu also has been smitten by the Elon bug as part of the Terafab project, stating on the earnings call:

We are excited to explore innovative ways to refactor silicon process technology, looking for unconventional ways to improve manufacturing efficiency that will eventually lead to a dynamic improvement in the economics of semiconductor manufacturing.

Sure, you do you — as long as we can get 18A yield up here on earth before we start building fabs in space.

Marvell announces acquisition of Polariton for Plasmonics

You can’t take your eye off the optics ball with all these CPU/TPU distractions. Marvell continues its spree of acquiring photonics companies as it continues its march toward next-gen 3.2T networking, by announcing the acquisition of Polariton Technologies — a Swiss startup.

It’s too late in the week for heavy physics, and we’ll do that in a future deep dive. Let’s look at this cool picture first. This is what Polariton does.

You can send an optical signal through an electro-optic dielectric material sandwiched between two metal electrodes. When you provide electrical 0s and 1s on one of the metal electrodes, the electrons on the metal interact with the light flowing through the dielectric waveguide causing Surface Plasma Polaritons (SPPs). These things affect the phase of the light creating highly effective, and very tiny, phase shift modulators.

The small size of this thing has two advantages:

1. Low parasitic capacitance, which means you can modulate at high speeds.

2. Much lower power dissipation

It’s so interesting when wave-particle interaction physics is hitting mainstream applications. I guess we’re really pushing technology now.

Have a great weekend!

The networking industry has been making rapid strides towards Co-Packaged Optics (CPO) for scale-out networking with external lasers, replaceable 3D optical engines, and per-lane data rates of 200G or more. Traditional arguments against CPO such as laser failures and serviceability are no longer show-stoppers, as explained later in this post. Still, CPO is an architectural reset that upends the traditional pluggable optics market and consolidates various networking components into the hands of a few suppliers like Nvidia, Broadcom, and Marvell.

This paradigm shift puts immense pressure on pluggable transceiver manufacturers like Eoptolink, and system integrators like Arista Networks. As optical functions shift to advanced silicon packaging using TSMC’s CoWoS and COUPE, the value chain moves away from traditional PCB assembly and rack integration. In a defensive play to protect their margins and market share, these players are responding with a new format of their own.

At OFC 2026, Arista Networks introduced eXtra-dense Pluggable Optics (XPO) for AI data centers. XPO keeps the existing pluggable approach, but scales it for higher bandwidth and better thermal management. The XPO multi-source agreement (MSA) now has >100 participating companies, including Marvell (playing both CPO and pluggable sides), Lumentum, Coherent, and Eoptolink - a sign that the industry is serious about this.

In this article, we’ll cover three things:

1. A primer on the XPO format and how it solves the faceplate bottleneck

2. The three-way trade-off between speed, power, and modularity that decides CPO versus XPO at each generation

3. Why CPO and XPO formats will coexist in scale-out at 1.6T but diverge as lane speeds climb to 3.2T and beyond.

We’ll conclude with a view on where each format lands across scale-up, scale-out, and scale-across, and why multiple strategies will likely coexist for years.

This post will have a lot of optical terminology. If you are unfamiliar with it, please see an earlier post below that explains most of what you need to know.

If you are not a paid subscriber, you can purchase just this article using the button below. You can find the whole catalog of articles for purchase at this link.

Buy the ebook

How XPO Solves the Faceplate Bottleneck

As switch ASICs scale toward 204.8T, the physical real estate of the switch faceplate becomes a severe bottleneck. The traditional pluggable model simply runs out of physical space. Consider the math for outfitting a 204.8T switch with standard 1.6T OSFP modules: a standard 1OU (Open Rack Unit) slot accommodates about 32 OSFP plugs, delivering 51.2T of bandwidth. Fully outfitting a 204.8T switch therefore requires 4OU of rack space purely for front-panel connections.

XPO alters this physical footprint entirely. An XPO module delivers 12.8T of bandwidth, or eight times the capacity of a 1.6T OSFP. While the XPO form factor is roughly 2.7x wider (allowing only 16 plugs per 1OU), those 16 plugs can deliver the full 204.8T in that single rack unit.

The core advantages of XPO:

• 4x Density Gain: It reclaims 3OU of highly valuable rack space per switch, reallocating it back to CPUs and GPUs at the datacenter level.

• Reduced Component Failure Domain: Just 16 XPO plugs replace the DSP, transimpedance amplifier (TIA - that amplifies the detected signal), driver, and photodetector components that would otherwise be spread across 128 OSFP plugs.

• Supply Chain Continuity: It retains the external, modular approach hyperscalers are accustomed to. MSAs ensure a diverse supply chain, and the format supports any optical interconnect reach (DR, LR, ZR, ZR+) and technology (IMDD (intensity modulation direct-detection), coherent, coherent-lite, micro-LEDs, and RF).

DSP Power and Cooling in XPO

The primary downside to XPO’s pluggable format is dealing with signal degradation over copper interconnects between the faceplace and switch ASIC using power-hungry DSP chips. XPO offers three implementation paths to manage this, in decreasing levels of power consumption:

1. Full Retimed: Utilizes a DSP on both the transmit and receive sides (highest power).

2. Linear Receive Optics (LRO / Half-Retimed): Utilizes a DSP only on the transmit side, saving power while maintaining signal integrity.

3. Linear Pluggable Optics (LPO): Eliminates the DSP entirely, relying only on drivers and equalizers, leaving the heavy lifting to the switch ASIC (lowest power).

Regardless of the DSP architecture, XPO’s immense bandwidth density makes traditional air cooling impossible. Liquid cooling is essential. Each XPO plug features an integrated cold plate designed to dissipate roughly 400W. While some legacy solutions attempt to bolt cold plates onto the exterior of OSFP plugs, XPO’s natively integrated liquid cooling is vastly more efficient. This also implies that the racks in the datacenter using XPO need to have liquid-cooling available, which might be difficult in legacy infrastructure.

In comparison, CPO boasts the lowest power consumption per port across the board. Because optical-to-electrical conversion happens directly adjacent to the switch silicon, CPO bypasses the need for heavy external DSPs. How XPO ultimately stacks up against CPO economically depends heavily on which of the three XPO implementations - Full, LRO, or LPO - a data center adopts.

Approximate numbers; varies based on vendor and implementation.

That sets up the real question: which format actually wins, and where? The answer depends on how hyperscalers weigh three trade-offs that diverge as we push to higher lane speeds: speed, power, and modularity.

After the paywall:

• A deep dive into the trilemma of speed, power, and modularity that dictates whether CPO or XPO wins in future networks.

• A detailed breakdown of CPO’s superior energy efficiency, how serviceability concerns are solved, and its market impact on the pluggable optics ecosystem.

• An analysis of the XPO-LPO and XPO-LRO “Goldilocks” approaches for 1.6T networking, and their limitations on lane speed and supply chain concentration.

• A look at the divergence point: why XPO becomes power-prohibitive at 3.2T and beyond, making CPO the more attractive future-proof architecture.

• The final verdict on where CPO makes the most sense (scale-out) and why XPO is the natural fit for scale-across networks.

Read more

Here’s what you might have missed this week:

• Tokenmaxxing and the Token Value Chain

• Is Intel Finally Back with a $300B market cap? OpenClaw can Dream?

Now, on to the news.

Credo agrees to acquire Dust Photonics

This is perhaps the biggest piece of news this week with many substacks covering it. We won’t get into the depths of the deal because a simple search will uncover a wealth of takes which you can read. I’ll only touch on a few important points here.

Dust Photonics provides photonic ICs which integrates nicely into Credo’s SerDes experience making them a full-stack interconnect provider — from active electrical cables, pluggable optics, microLED cables, and now integrated photonics. This latest acquisition makes Credo an interconnect powerhouse in the AI era.

I’ve also maintained that Credo’s “zero-flap” metrology for link health is one of their biggest strengths, and is a software layer that really makes the interconnect layer work at scale. You’ll also notice that Marvell has a lot of parallels in the interconnect space here; SerDes expertise, optical DSP, photonics, and telemetry systems. Credo is a smaller player, and gives the big dog (MRVL) a run for its money.

I really like Gavin Baker’s (who runs Atreides Management, an investor in Dust Photonics) explanation of the acquisition in his tweet which you should read in its entirety.

The most important take-aways from what Gavin said is that copper and optics is not a zero-sum game. Copper will remain relevant well into the 2030s, and optics will play an increasing role in datacenters. He identifies scale-up as the area for most networking growth (note that it need not be optical), followed by scale-across (this was surprising to me), and finally scale-out (which might involve CPO at some point). All this while laser shortage is getting worse!

He calls out that Credo’s Hyperlume acquisition was a smart bet, and that there is a lot of positive feedback about MicroLEDs as viable interconnect tech. We’ve started covering microLEDs on this newsletter (free post below). Also, the upcoming Semi Doped episode has a longer discussion on the Credo acquisition. Stay tuned!

(via Credo)

Thoughts on the CPU Shortage

We’ve covered the need for CPUs in agentic AI in quite some depth, and the article below has been the most popular, highest earning article YTD. We called out early that CPU:GPU ratios are going to go to one, or higher.

Since the two months that the article was published, the CPU shortage has gotten worse — to the point that cloud service providers that have nothing to do with AI inference are falling short of CPUs. The x86 vs ARM argument does not really even matter anymore. CSPs and hyperscalers will take anything they can lay their hands on, and port over software if they have to.

The situation is dire enough that the winner in CPUs is anyone who will execute on the manufacturing side and provide sufficient CPU supply. Things like core count vs IPC, or reasoning vs action workloads, or what CPU is best suited for an end application is all moot now. Sadly, most of the supply chain squeeze for CPUs also depends on what TSMC can deliver, and their ~$60B 2026 capex spend has been argued to still be too conservative for the number of chips we need. The ace in the hole would be if Intel can deliver server CPUs at scale purely on 18A.

Nuvacore: Engineered for Altitude

Speaking of CPUs, Nuvacore is a new CPU company funded by Sequoia capital, with the promise below:

A general-purpose CPU core designed to excel everywhere—from core infrastructure to advanced AI systems, including the continuous demands of agentic computing.

This is not iteration, it is a complete rewrite of the rules of silicon.

The brains behind this operation are Gerard Williams, John Bruno, and Ram Srinivasan, whom you may know from Nuvia - a company Qualcomm bought in 2021 and used their IP for their Oryon series of desktop ARM processors. The ARM licensing agreement used in this product was a matter of big contention, which was hotly contested in courts. All three founders left Qualcomm earlier this year, and Nuvacore was born.

Here is what is exciting about this news: Nuvacore promises to rethink how CPUs are built for everything including the agentic AI era. While an earlier post on this newsletter discussed the “most desirable” features of an agentic CPU across 9 different metrics, it is interesting what these CPU legends think is important for AI. More cores? More performance per core? Special architectural decisions? We have to wait and see.

(via nuvacore.ai)

NAND Shortage is Real; Phison fires warning shot

Digitimes reports that Phison CEO, Pua Khein-Seng, warned that NAND flash shortage is going to significantly worsen towards the end of 2026. It has led the company to break its 26 year old tradition of “no-debt” by fundraising a total of $1.4B for 2026. Supply tightness is expected to extend well into 2028, possibly beyond.

Note that Kioxia recently ended the production of older SLC and MLC NAND to prioritize higher margin TLC and QLC NAND SSDs for AI applications. I’ve had multiple discussions with professional investors this week about NAND, and I’ll be digging deeper into the demand for NAND in a future newsletter article. If you need a refresher, check out an older post.

(via digitimes)

Largan won’t make camera lenses for Apple, becomes CPO pilled

I like it when strange things happen — things outside the norm. In what sounds like a little guy finally standing up to the big bully, Largan Precision has said that it won’t increase order volume for the Apple iPhone 18 Pro, instead choosing to focus on optics for CPO.

Largan is a major provider of optics to Apple, but the recent move against Apple indicates an aggressive business pivot from a high volume, low margin smartphone business to high margin, potentially hyper-growth AI optics sector.

It’s a high risk gamble especially since Apple is buying up all the DRAM available at elevated prices to lock others out of the Android market. This shows that Apple is pretty confident that the memory prices are not going to affect their smartphone sales. Yet, Largan is willing to walk away, leaving the pieces to be picked up by competitors such as Sunny Optical (2382.HK) and Genius Electronic Optical (GSEO/TPE:3406). Incidentally, GSEO got a nice stock price bump right after the news of the rebuke broke. Not entirely sure if these companies can fill Largan shoes for iPhone orders.

(via wccftech)

Meta’s now-defunct “Claudeonomics” leaderboard ranked employees by token usage, while celebrating power users with titles like “Token Legend.” In a 30 day window, company-wide consumption topped 60 trillion tokens, with the top contender alone burning 281 billion. CTO Andrew Bosworth bragged publicly that his best engineer was spending the equivalent of his salary in tokens and getting up to 10x more productivity out of it. How productivity was measured remains unknown. On the All-In podcast at GTC, Jensen said that if his $500K engineer was not consuming at least $250K worth of tokens, he would be “deeply alarmed.” Silicon Valley engineers tell me their companies are pushing the same tokenmaxxing message internally. But if the number of tokens used becomes the target, it stops being a useful metric (Goodhart’s law).

Here’s what you have to pay attention to: the tokenmaxxing message applies to those who are able to establish a linear (preferably exponential) relationship between outcome and token usage. Tokenmaxxing can be rational, but not always.

Foundation model providers like Anthropic and OpenAI have a clean, understandable revenue metric (pay-per-token). Meta has massive internal workloads like serving ads that require internal token consumption. Garry Tan wants software startups built faster at YC. Nvidia and AMD simply want to sell more hardware.

In this post, we will examine the promise of the Token Value Chain, how reality is more nuanced, who stands to benefit, and who stands to lose. More importantly, we will discuss what a “smart token” strategy should look like for companies looking to go AI-native, and when tokenmaxxing is a viable strategy.

If you are not a paid subscriber, you can purchase just this article using the button below. You can find the whole catalog of articles for purchase at this link.

Buy the ebook

The Token Value Chain

The token value chain is simple: massive amounts of wealth injected into the top of the chip manufacturing supply chain will flow through token providers, and ultimately manifest as profit for enterprises adopting AI through dramatic increases in productivity (products shipped, revenue earned, etc.).

The Token Value Chain has three levels:

1. Token Supplier: Nvidia and AMD sit at the top of this tier selling GPUs, but the real supplier base is much wider: CPUs, memory/storage, interconnects (copper/optics), PCBs, and power/cooling. Neoclouds like CoreWeave and Nebius belong here too, renting out GPU capacity by the hour. Every single token burned is a pick-and-shovel sale for this tier. Revenue scales with volume, supply chain and power bottlenecks not included.

2. Token Provider: Anthropic and OpenAI do most of the work, with Google, xAI and a handful of others in the mix. These are the companies that take raw compute from the Supplier tier and turn it into tokens sold on a pay-per-use basis. Every token they produce is money, which is why Anthropic’s revenue run rate has gone from $1 billion to $30 billion in about 15 months. Revenue here also scales with volume. The more their customers tokenmaxx, the better the numbers look.

3. Token Consumer: Enterprises, startups, and increasingly every Fortune 500 company that has been told to go AI-native. It is also the only tier in the value chain whose revenue is not tied to token volume – at least not directly, and not always.

The promise of AI is that massive amounts of investments into the Supplier tier translates into more tokens generated by Providers, which ultimately leads to massive profitability at the Consumer level, which will then recursively feed the massive infrastructure spend at the Supplier tier. If you look closer, the Provider layer revenue is tied to token volume, which translates to volume in Giga-Watts deployed at the Supplier tier. But the Consumer pays the ultimate token price.

Gavin Baker puts this eloquently in an interview at Nvidia GTC.

If you are not a token producer, your fate as a business is going to be entirely determined by how efficiently and effectively you consume tokens as an organization.

In other words, while the cost per token used is pre-determined, the revenue generated per token used is anybody’s guess. While both the Supplier and Provider win on volume, the Consumer has to win on outcome. If you view tokens as the raw materials required to produce a product, then there are two approaches to run the business:

1. Use as little raw material as possible to produce products, and increase margins. A token-constrained consumer would use an intentional token deployment strategy and ride the efficient frontier of intelligence per token used. A number of “smart token strategies” can be deployed to get the “most bang for token buck.”

2. Use as much raw material as possible to generate as many products as possible and corner the market. A token-rich consumer would deploy an infinite number of tokens of a leading intelligence model without regard to token cost, to produce remarkable results; just like infinite monkeys with a typewriter can produce Shakespeare. In theory, infinite intelligence (and money) would automatically lock out competitors, leaving token-constrained entities unable to compete. This is tokenmaxxing as a strategy.

We’ll expand on these two ideas after the paywall.

Read more

We’ve covered a lot this week, and in case you haven’t had a chance to catch up.

• MicroLEDs vs Lasers: The Linewidth Tradeoff — why linewidth matters and how LEDs and lasers differ (no paywall this week, enjoy!).

• Busy week on the Semi Doped podcast (which crossed 10K downloads!):

  • NVIDIA’s Marvell Strategy, Is Memory Different This Time?, Intel’s Ireland Fab

  • $300M for 70K Viewers | Intel x Elon, OpenAI x TBPN, Citrini’s Strait of Hormuz Stunt

  • Austin interviews Reiner Pope from MatX

Alright, let’s dive into the news.

Intel Joins Musk’s TeraFab Project

Intel announced it will join Elon Musk's TeraFab project alongside SpaceX, xAI, and Tesla. The Terafab project aims to produce 1TW of compute capacity annually and Intel would bring its expertise in advanced nodes, packaging, and silicon manufacturing at scale.

If Musk actually delivers on even 10% of TeraFab's ambition, Intel secures a whale customer, a strategic win, and a major turnaround. For the Terafab project, Intel being involved actually brings in a practical level of feasibility than Tesla/SpaceX/xAI trying to build a leading-edge fab from scratch.

This is a win-win for both parties involved but will have material impact only when we see significant wafer starts per month from Intel towards the Terafab project.

Heterogenous systems for Agentic AI: Intel + Sambanova

On other Intel news, from the press release,

SambaNova today announced the next phase of its collaboration with Intel: a heterogeneous hardware solution that combines GPUs for prefill, Intel® Xeon® 6 processors as both host and “action” CPUs, and SambaNova RDUs for decode to deliver premium inference for the most demanding Agentic AI applications.

Just like we saw Nvidia pair Rubin GPUs with Groq LPUs and Vera CPUs, Intel and Sambanova are collaborating to provide specialized decode hardware and CPUs. Their comparison table below is interesting and points out something important: the number of decode chips required.

One of the major limitations of LPUs is its limited SRAM and the need to deploy thousands of chips for large models. The complex compiler architecture of Groq chips means its not easy to add HBM/DRAM to expand capacity at the expense of speed. This inelasticity is why I have believed that Groq LPU was never a good fit long term, regardless of how much Nvidia paid for them.

Sambanova’s SN50 RDU architecture uses SRAM, HBM and DRAM, but their secret sauce is to “predetermine” where each piece of the information is going to come from in advance. The RDU stands for Reconfigurable Data Unit, and it establishes a data path between different heterogeneous storage media to access data. This makes it vastly more flexible than Groq’s static approach. MatX also uses a hybrid SRAM+HBM system that is super interesting (check out Austin’s interview with the CEO linked above). We discussed all this in a previous TWiC edition.

This is just the first of many such heterogeneous solutions that will emerge. The effectiveness of each solution will depend on how data movement is architected between various pieces of disparate hardware. Exciting times.

(via Sambanova)

Intel + Google partner on Xeon CPUs and IPUs

In even more Intel news, Google and Intel partner to deploy Xeon CPUs and Infrastructure Processing Units (IPUs) for AI workloads. IPUs handle networking, storage, and security, much like Bluefield Data Processing Units (DPUs) from Nvidia. The main idea is to offload some admin functions from the main CPU so that it can focus on more critical AI related orchestration tasks.

In a way, this shows that not all CPUs are headed the ARM way, and x86 retains its stronghold in AI datacenter deployments. Google’s own ARM-based Axion CPUs were deployed for cloud infra and were focused on energy efficiency. In the AI era, raw power still matters and x86 Xeons still crush. If you want a head-to-head comparison CPUs in the market, check out our CPU yellow pages.

(via Intel)

Samsung Projects Record Q1 Profit, Driven by Memory

Samsung is projecting a blowout quarter with a 755% YoY increase in profits of 57T won ($38B) compared to 6.7T won ($5B) in Q1 2025. 95% of the profits are from the memory sector, while the rest is from other sectors like mobile which are flat or declining. Revenue is up 68% YoY. It is anticipated that other major players like SK Hynix and Micron will post spectacular results in the coming quarter too.

We are now deep in the memory supercycle since we first spoke about it on this newsletter six months ago.

In this week’s Semi Doped podcast, we discussed how spot DRAM prices are so high due to AI sucking up all the supply that consumer devices are left scrambling to get what silicon is left over. While this has led to memory price crashes in the past, we argued in an article to paid subscribers how this time is different because of a structural demand enforced by AI, regardless of algorithmic improvements such as TurboQuant.

Samsung’s projected numbers in Q1 2026 are validation of growing memory demand and DRAM/NAND price hikes that are still rising in the coming quarters. But notably, a large portion of the ~8x profit increase is coming from the DRAM market, and not necessarily HBM. This is worrisome because while HBM provides a structural floor, spot prices are far more volatile and things often turn around quickly.

Anthropic Hits $30B Revenue Run Rate, Overtakes OpenAI

Anthropic revealed a $30B annualized revenue run rate, triple the ~$9B at end-2025 and up from ~$19B in March. They simultaneously announced a deal for 3.5GW of Google TPUs (via Broadcom) starting 2027, adding to ~1GW already secured.

30x ARR growth in 16 months makes Anthropic the fastest-scaling enterprise company in history. But the infrastructure story is equally significant: they're hedging across AWS Trainium, Google TPUs, and NVIDIA GPUs — a diversified compute strategy. This is a big plus for Broadcom which now has a >$100B AI pipeline (possible $200B?). In a weird turn of events, Anthropic is rumored to start developing their own chips. What else are they gonna do with the extra change when their ARR hits $100B next month? 🤡 (or maybe not?)

Arm’s Strategy of Selling AGI CPUs to China

This bit of news is slightly over a week old, but I feel it flew under the radar. Arm’s CEO Rene Haas said in an interview to the ChinaDaily that Arm intends to sell its finished AGI CPU to Chinese customers. US/UK export controls restrict Arm from licensing its Neoverse V3 cores, but says nothing about selling finished chips instead of just IP. This is a key distinction: licensing IP would let Chinese firms design and produce their own chips indefinitely; buying finished CPUs from Arm does not transfer that design capability.

Selling CPUs in China unlocks a huge market that previously did not exist for Arm. The AGI CPU gives Chinese buyers immediate access to a modern, high-core-count, AI-optimized Arm server processor for orchestrating large AI/agentic workloads. The key announcement to now track is Arm’s first Chinese CPU customer, whoever that is.

(via ChinaDaily, DigiTimes)

Have a great weekend!

A useful starting point to understand the lasers versus LEDs debate is to ask what linewidth is, why it matters, and how lasers and LEDs broadly compare. Let’s first describe the technology landscape.

You can download this post in epub or pdf formats for free using the button below. If you are not a paid subscriber, and would like to purchase individual articles, please see the catalog here.

Get as free ebook

Lumentum, Coherent, and DFB Lasers

Distributed Feedback (DFB) lasers often made from Indium Phosphide (InP) are known for their narrow linewidth, where Lumentum holds dominance in 200G/lane electro-absorption modulated lasers (EMLs). Their moat comes both from having a great laser source and a co-optimized modulator that encodes high-speed electrical signals into light. The performance gap in EMLs is seemingly wide enough (specs not published widely) that their competitor, Coherent, actually buys these EMLs from them. This puts Lumentum in the driver’s seat for EMLs in the 1.6T optical era involving pluggable transceivers.

A DFB laser for co-packaged optics (CPO) is a different beast and is a space where Lumentum has serious competition. CPO requires a constant source of light (called continuous-wave or CW) because the modulation is handled by the silicon photonics chip using a ring or Mach-Zehnder modulator. Here, a constant output power of 300-400mW at elevated temperatures of 50-70°C is the key differentiator. This level of output power is needed because the light source is outside the rack, and connected to the SiPho chip via a long polarization maintaining optical fiber. We’ve discussed this earlier.

Laser Linewidth, RIN, and Power

Lumentum’s ELS laser for CPO has an advertised output power of 350 mW at 50°C, a line width of <500 kHz, for a 1311 nm laser. Coherent’s equivalent laser has a reported output power of 400mW at 50°C and a linewidth of <200 kHz. Linewidth is a measure of how pure the light source is, and is quantified by the Full-Width at Half-Maximum (FWHM). Take the maximum laser power, cut it by half and measure the spreading of the laser frequency/wavelength. The smaller this number, the more pure the laser output on the spectrum.

Anything under 1 MHz in linewidth is exceptionally pure light, really. A 1311nm laser translates to about 230 THz in free space which is really narrow compared to the center frequency. The deviation in wavelength is so small that laser engineers prefer frequency units to represent this. This is the magic of DFB lasers.

Lasers from both companies have a Relative Intensity Noise (RIN) of -145 dB or thereabouts. RIN is a measure of how stable the output power is. Think of a bad laser with high RIN as flickering too much. Lumentum is not much better in RIN; the frequently cited -156 dB RIN for Lumentum is a hero number from a CLEO 2022 paper. Their production RIN is in the same ballpark as Coherent. Thus, while Lumentum has a clear advantage in EMLs for pluggables, the race to CPO lasers is highly contested (there are other players but their laser specs are not publicized).

Regardless of lasers for pluggables or CPO, the key takeaway is that DFB lasers with their narrow linewidth are perfectly suited for optical communication, and have been the mainstay for long haul links. They allow encoding of fast data signals and have long distance reach. Here is the critical question: is DFB laser the right choice of technology for short-to-medium distance optical links in a datacenter?

The Case for MicroLEDs: Benefits and Challenges

There has been a slew of activity around the use of Micro Light Emitting Diodes (LEDs) for data transmission. Credo moved to acquire Hyperlume last year, Microsoft published results from Mosaic, and Marvell most recently is collaborating with Mojo Vision on microLEDs. We would be remiss if we did not mention Avicena, who has been pioneering MicroLEDs for AI interconnects for a long time.

MicroLEDs are just really small versions (10-50 microns in size) of your regular lightbulbs, and are built with Gallium Nitride (GaN) to emit blue light. Just like you don’t get a laser light show every time you walk in your room and turn the light on, microLEDs do not emit a narrow pencil beam of light like lasers. They instead produce light in a wide angle and need to be focused with a microlens. The light is not spectrally pure like lasers either. Blue GaN microLEDs have a wavelength of about 450nm, and linewidths of 10-15nm. Compared to lasers, this is terrible linewidth because it accounts for about 3% around the center wavelength.

The poor linewidth in comparison to lasers imposes restrictions on data rate that a microLED optical link can support. The solution around this is to use an array of microLEDs in a “wide-but-slow” approach – just like each data lane in high bandwidth memory (HBM) is slower than what is possible in GDDR, but the overall throughput is higher. There are a few additional benefits of using microLEDs:

1. Lower power than DFB laser optics (caveat to follow), but better reach than copper (can possibly do >10m at Tbps aggregate speeds)

2. Better reliability than lasers because LEDs are structurally simpler, and relatively temperature insensitive. A wide-but-slow approach means that there could be redundant lanes for failover.

3. Linear path to scaling to higher speeds: increase per-lane speed (harder) or increase number of lanes (easier).

While microLED cables would work directly with existing pluggable infrastructure, there are two important requirements that makes things more complex:

Focusing optics

The broad angle emission from a microLED needs to be focussed with microlenses in order to couple them into an array of optical fibers that carry multiple parallel lanes of data. In reality, this is not difficult because microlenses are also implemented as an array that fits directly over the microLED array. DFB laser sources have specialized optics to couple light into fibers too.

Electrical Gearboxing

You need an “electrical gearboxing” function that converts the 112G/224G narrow-but-fast SerDes lanes of the host processor into a 20 x 20 microLED array that carries slow-but-wide signals at lower data rates. This chip is implemented as a CMOS ASIC that handles the electrical gearboxing. For example, the Avicena LightBundle™ evaluation kit launched at OFC 2026 uses a specialized 16nm finFET CMOS ASIC. The only way a gearbox chip can be avoided is to design the host processor with a UCIe interface that natively implements a wide-but-slow approach (like a custom base-die used in HBM).

Microsoft’s paper on microLEDs shows that the gearbox functionality only consumes a small portion of the power (0.4W) it would otherwise take with an optical connection that requires DSP/CDR/FEC (3.5W). The argument in the paper is that it is a simple gearboxing function, and thus less power hungry. If per-lane speeds increase in future generations of microLED interconnect, then CDR/FEC functions will be required and power usage will increase, closing the power efficiency gap between lasers and microLEDs.

Why linewidth matters for data rates

Let’s address why microLEDs are only capable of 2-4 Gbps data rates today in pre-production, while DFB EMLs can support 200 Gbps or more.

The fundamental concept that underlies this limitation is chromatic dispersion in an optical fiber. When an optic signal travels through a fiber, different wavelengths travel at different speeds due to the wavelength-dependent refractive index of glass in the fiber. The resulting pulse exiting the fiber spreads out in time because different wavelengths arrive at different times.

This spreading determines the maximum speed of data transmission that is possible because once neighboring pulses start to overlap, it is hard to tell them apart and detection errors start to occur.

The broadening of a pulse by a time dT (ps) in an optical fiber can be calculated as

Where D is the dispersion coefficient in ps/(nm·km), L is the link length in kilometers, and is the linewidth of the light source. Assuming Gaussian pulses are being transmitted as bits, the data rate Bmax is:

Let’s try out some numbers here.

With a microLED

A standard legacy multimode optical fiber (such as OM3 or OM4) operating at 850 nm exhibits a material dispersion parameter of approximately 100 ps/nm/km.n For an 850 nm microLED with a spectral linewidth of 40 nm (4.7% of center wavelength), operating over a link length of 0.010 km (10 meters), the temporal pulse spread is calculated as: 100×0.01×40, or 40ps. Maximum data rate supported = 0.44/40ps = 11 Gbps/lane. These speeds have been demonstrated in research papers with microLEDs, but production numbers are slower at 2-4 Gbps/lane.

With a DFB laser

Let us assume the same wavelength, and same link distance, but a linewidth of 0.001nm. The temporal pulse spread is: 100×0.01×0.001 = 0.001ps. Maximum data rate supported = 0.44/0.001 = 440 Gbps/lane.

This demonstrates why linewidth makes a big difference in how much data rate is possible with a given type of light source in an optical communication system.

There is a lot more to discuss about microLEDs before we can declare microLEDs fit/unfit for datacenter needs: coupling efficiency into fibers, beam shapes, reliability assessments, and the overall supplier/customer landscape that is still rapidly evolving.

Industry sources tell me that hyperscalers are open to exploring microLEDs for future interconnect needs, but the microLED industry for datacenter interconnects is still young. An additional aspect worth exploring is how VCSELs compare as an alternative to microLEDs – something that Lumentum is actively exploring with 1060nm VCSELs. So many future post options!

Here’s the post if you haven’t gotten to it yet.

In last week’s Semi Doped podcast, we covered TurboQuant in some detail, and argued whether Arm’s AGI CPU will actually displace x86 in the long run.

• ARM AGI CPU has entered the chat, TurboQuant thrashes memory stocks

Now, on to the news.

Samsung Enters SiPho, Wants to Connect HBM with Light

Samsung unveiled its SiPho Foundry platform at OFC 2026 that is production-ready, with a PDK, and ready for manufacturing on a 300 mm wafer process. The main pitch here is Samsung’s vertically integrated memory capabilities with HBM and silicon photonics under one roof, a turnkey bundle that TSMC cannot match. Early results are expected in the 2028-29 time frame, and the industry places Samsung roughly 3 years behind TSMC, primarily due to ecosystem, design enablement, and customer trust. Samsung’s Semiconductor division has already designated its silicon photonics processes as “I-CubeSo” and “I-CubeEo” (try saying that 3 times in a row) and is allegedly working closely with Broadcom and Marvell.

(via The Elec, DigiTimes)

Low/mid tier mobile is driving demand destruction; PC demand down

MediaTek and Qualcomm are both cutting 4nm chip shipments by 15-20 million units combined because memory has gotten so expensive that low-to-mid-tier smartphones make no sense to build because their BOM is so high. Whether premium tier phones are insulated is questionable, especially when Apple is supposedly buying up all available DRAM at high prices to starve out Android competitors like Samsung (ironic since Samsung is also Apple's largest DRAM supplier).

Last year, more than 360 million smartphones shipped below $150, representing a substantial share of global volumes, with that proportion rising in key emerging markets like Africa and India. The push for greater economies of scale will drive mergers among the smaller players. Omdia cites Realme reintegrating under OPPO's umbrella as early signs of consolidation as vendors seek greater scale to manage rising costs. The consensus is that this is a structural reallocation of memory capacity toward AI/HBM at the expense of consumer TAM.

Nvidia joins forces with Marvell via NVLink Fusion

Nvidia and Marvell announced a partnership that allows Marvell’s custom ASIC silicon to run on Nvidia infrastructure via NVLink fusion. Market sentiment is overwhelmingly positive on this news, and Marvell shares surged 13%. The deal is viewed as a defensive masterstroke by Jensen that signals that if Nvidia can’t beat the custom chip movement, they can at least own the fabric ASICs run on. Clear winner is Marvell here because they get the $2B investment cookie that Nvidia has been handing out to everybody (LITE, COHR, NBIS…) and also “preferred partner” status with Nvidia. This puts Broadcom in a more challenging position as the primary backer of UA-Link standard over NVLink fusion.

(via Nvidia News)

Intel buys back 49% share of its Fab 34 Ireland fab

Intel said it would spend $14.2 billion (cash+debt) to buy back the 49% stake it sold to Apollo Global in its Ireland manufacturing facility. The fab produces leading-edge nodes like Intel 3 and 4, including its Core Ultra and Xeon 6 processors. The price paid is $3B more than they sold it for two years ago, and the market is reading this as Intel’s conviction in their foundry strategy by putting real money behind the chip manufacturing. The sentiment is strongly positive and is interpreted as a sign of confidence that Intel’s foundry turnaround is actually happening. Investors will closely scrutinize whether the strategic benefits are strong enough to justify the added cost and financing burden.

(via Intel)

OpenAI closes record breaking $122B funding round

Total valuation is $852B. Seriously, that is a lot of money. OpenAI is pulling $2B/mo in revenue, and still continuously losing money. Only profitable in 2030. 👀

(via The Guardian)

Anthropic’s Claude has a wardrobe malfunction

Claude’s source code leaked via npm repository, and yeah, we can see everything underneath 🙈, including a digital pet and an always-on agent. The funniest coverage on this is from ThePrimeagen on YouTube. Seriously watch it lol.

(via literally everywhere)

Your latest co-worker is now an AI employee

This is a $2,000/mo AI from a company called Kuse AI that is a virtual AI employee who never sleeps, eats, or goes to happy hour. There are 2,000+ companies who have signed up for the wait list. If companies need to pay 3-5x more for a human who demands work-life balance, an OpenClaw agent that the company calls Junior seems to be a better bet. All well and good, but you can’t choke an AI neck when things go wrong.

(via Bloomberg)

Atlas Studio: A Foundation Model for Electromagnetics

This is a physics foundational model that is useful for a lot of RF design work that would take too long with a simulator. Not Boring has a long piece on it. Long time readers would remember a piece I wrote about crazy RF designs from Prof. Sengupta’s group (Princeton) last year. Well, Prof. Sengupta is now pushing back on the ‘radicalness’ of the foundation EM model by comparing it to someone claiming that they invented the transistor.

(h/t @SinghJyotirmai, via Arena Physica)

PrismML: 1-bit Bonsai 8B model fits into 1.15GB

With the TurboQuant meltdown in place, I wonder if we should worry about dramatically compressed models like PrismML. If this delivers any level of useful intelligence, it could unlock a whole new world of edge inference. Its open-source and extremely light weight for an 8B parameter model. I think I’ll run it on my Mac M3 pro this weekend and see how I like it. I already tried it on my iPhone. It could also serve as a local fallback model for OpenClaw.

(via PrismML)

Have a great weekend!

Still, worries of TurboQuant wrecking the memory industry have not abated. To the contrary, a new fear has been unlocked: the peak of the “hog cycle” often seen by seasoned investors as a strong signal of a memory peak, and impending doom.

The counterargument is that “this time is different,” driven primarily by the insatiable demand for memory in AI deployments, and the token explosion in the era of agentic AI that is already here. The real question is whether the demand is high enough to serve as a fallback when the consumer segment finally “says no” to the extraordinary price hikes and cancels deployment of low/mid tier devices, and/or downgrades product specs to accommodate what memory is reasonably available.

In this article, we will investigate these arguments in greater detail, make reasonable guesses and inferences where possible, and attempt to have a balanced, realistic stance based on the current state of the industry.

Broadly, we will follow this line of inquiry:

The classic memory hog cycle isn’t dead — but AI has added a multi-layered structural floor that mutes the traditional ‘PC/smartphone makers say no’ warning signal and turns the 2026 pullback into a buying opportunity rather than the start of another 2019/2022-style bust.

Here is what we cover:

• Hog Cycles as a Leading Memory Indicator

• 2026: PC/Smartphone Industry Says ‘No’

• “This Time is Different” – But is it?

• 🔒Understanding the New AI Realities

• 🔒Memory as the Bottleneck

• 🔒Revisiting the Thesis and Risks

If you are not a paid subscriber, you can purchase just this article using the button below. You can find the whole catalog of articles for purchase at this link.

Buy the ebook

Note: This article does not constitute investment advice. Do your own research.

Hog Cycles as a Leading Memory Indicator

The classical hog cycle works like this: High pork prices lead farmers to breed more pigs. By the time the pigs mature, the market is flooded, prices crash, farmers stop breeding, and a shortage ensues and causes prices to spike again.

This applies directly to memory. A new technology (smartphones, cloud computing, AI) drives massive memory demand and prices soar. Memory makers enjoy record margins and heavily invest in expanding fab capacity. It takes years for that new capacity to come online. During this time, buyers double-order to secure supply, artificially inflating demand. The new fabs finally start producing exactly when downstream demand begins to cool. Supply floods the market, inventory piles up, and prices crash below the cost of production.

This cycle has specifically played out at-least twice in the last decade.

• 2019 Cloud Burst: Datacenter boom for cloud computing and crypto mining lead to excess inventory when everybody suddenly stopped buying. DRAM prices plummeted by 50%.

• 2022 Covid Hangover: Covid-era shutdowns and the spike in PC/phone sales for remote work left OEMs with excess inventory that suddenly had no demand. The carnage was real: DRAM spot prices dropped >50%, server DRAM revenues collapsed, memory stocks fell 30-50%, and NAND sold for less than it took to make.

2026: PC/Smartphone Industry Says ‘No’

It seems like the memory downturn in the past week is one for the history books, largely driven by fears around TurboQuant, and more importantly another catalyst worth discussing: the PC/smartphone industry. Shares of Micron, SanDisk, SK Hynix, and Samsung are all down 20-30% from their recent peak. I’m guessing we will talk about this for years to come.

The PC/smartphone industry is the literal whale of the memory market consuming massive amounts of DDR, LPDDR and NAND flash storage. They have largely been squeezed out of the memory supply chain of late due to large spikes in DRAM and NAND pricing primarily driven by shortages due to the huge demand in AI accelerators, which consume nearly 70% of global high-end DRAM production. The recent TrendForce memory forecast below shows why pricing has reached a boiling point.

The prices for nearly every type of memory and storage has nearly doubled in a single quarter, which means that memory alone is estimated to occupy nearly 25-30% of a PC/Smartphone bill of materials (BoM). Two other factors further compound problems:

1. The long term agreements for memory supply entered after the Covid era bust are coming to an end. Consumer OEMs are being forced into an open market where there is virtually no silicon left to purchase.

2. The timing is particularly devastating for the PC industry, as this hyper-inflationary spike collides directly with the Microsoft Windows 10 end-of-life hardware refresh cycle.

Dan Nystedt on X explains how the PC/smartphone industry has now drawn a line in the sand by planning “fewer (or zero) mid-to-low-end handsets in 2026.” – a sign often viewed by seasoned memory investors as a time to sell. IDC reports that global PC shipments are expected to drop by 11.3% in 2026, a revision that calls out a much larger drop than their 2.4% estimate a quarter ago.

Conventional wisdom and history lessons in the memory market dictate that the memory market has peaked. But, bulls argue the insatiable AI demand makes this time different.

“This Time is Different” – But is it?

The simple bull argument for the market is that the extraordinary demand for AI will soak up any short term demand decline by the PC/smartphone industry. That is, AI is a “fallback” when consumer demand drops and memory prices stay unaffected. But how valid is this?

This argument holds for now because memory makers are happy to divert production lines towards HBM and server-grade DRAM memory as Micron did by dropping the Crucial line of consumer-grade memory. This worked out well because Micron’s last earnings call guided for an 81% gross margin, which would exceed even Nvidia’s if they deliver. Their non-HBM product lines are also more profitable now, thanks to inflated spot market pricing. Spot pricing is a double-edged sword because in a deflationary market, the same product lines will drag down revenue.

Interestingly, history shows that there has almost always been a series of overlapping technology S-curves that acted as “fallback” and delayed (not avoided) the eventual memory market destruction.

Here are some examples.

2015-2016: Smartphone Maturation + Cloud Buildout

• The Softening: In early 2015, the global smartphone adoption curve began to flatten and the upgrade cycle started stretching from 18 months to 24+ months. PC sales were also in a secular decline. With softening demand, smartphone OEMs started aggressively pushing back on memory contract prices.

• The Fallback: The early cloud build-out meant that AWS, Azure, and Google Cloud were beginning to scale their massive data centers. This created a new, hungry sink for server DRAM and NAND SSDs, absorbing wafers that would have otherwise flooded the mobile and PC markets.

• The Crash: The crash came around early 2016 because cloud buildouts could not effectively absorb the PC/smartphone softening, leading to an inventory glut and prices plummeting.

2018-2019: Smartphone Decline + Crypto Mania

• The Softening: Smartphone sales went from slowing to actually contracting globally. At the same time, the memory prices from the 2017 cloud supercycle had gotten so high that smartphone OEMs actively decided to cap the amount of DRAM in their flagship phones to protect their profit margins.

• The Fallback: During the crypto mining boom, hyperscalers were buying server memory at a frantic pace, terrified of supply shortages. The 2017–2018 crypto bull run created an insatiable demand for high-end graphics cards, sucking up massive amounts of GDDR and standard PC DRAM.

• The Crash: By 2019, cloud hyperscalers realized they had massively over-ordered DRAM, and switched to inventory digestion mode. Then came the crypto winter. Bitcoin crashed when people realized it was unprofitable to mine crypto and the demand for graphics cards and GDDR evaporated overnight.

2022-2023: Post-Covid Demand Drop

• The Softening: By early 2022, everyone who needed a laptop or phone for remote work already had one. As inflation spiked, consumer spending on electronics completely froze. PC and smartphone OEMs hit the brakes hard, cancelling memory orders to burn through their existing warehouses of chips.

• The Fallback: There was none. Cloud hyperscalers were not on a spending spree for memory, and as a result, nothing softened the blow.

• The Crash: Because memory makers had aggressively built new fabs during the 2021 boom, the simultaneous collapse of both the consumer main market and the enterprise fallback created the worst inventory glut in the history of the memory industry, forcing memory makers into deep operating losses.

Memory cycles have mostly had an infrastructure buildout softening the blow when consumer demand drops. The question now is: will this happen again with the AI infrastructure buildout?

After the paywall:

• Understanding the New AI Realities: The four structural differences—memory density, wafer efficiency, allocation shift, and contract stickiness—that make current AI infrastructure demand fundamentally unique.

• Memory as the Bottleneck: Why memory, particularly for long context windows and inference, has replaced compute as the primary bottleneck in AI systems.

• Revisiting the Thesis and Risks: Evaluates the AI buildout as a structural floor for demand, and provides perspectives on the 2026 memory pullback and risks.

Read more