Welcome to the quiz edition of this newsletter! If you’re new to this publication, start here! The content published here every week is only possible with your generous support.

Here are the answers to Semi Pub Quiz #1. If you want to attempt the quiz before looking at the answers, here’s the original post.

#1

Dennard scaling enabled more transistors on a chip as gate length got smaller, but without increasing power density. But one parameter — fundamentally limited by thermal physics — refused to scale, setting a hard stop around 2005. Robert Dennard warned about this in his original paper, and how it would eventually spell the death of Dennard scaling. What is this parameter?

A. Sub-threshold Slope or Gate Leakage

Sub-threshold slope (SS) quantifies how effectively a MOSFET transitions from off to on in the subthreshold region. Ideal SS is 60 mV/decade at 300 K.

Robert Dennard and his co-authors noted that subthreshold slope does not scale even if more transistors can be crammed into a chip while keeping power density constant. The increasing gate leakage right around when gate lengths reached 90 nm in 2005, spelled the end of Dennard Scaling. If you answered gate leakage, that’s fine too.

#2

According to its founder, Lee Byung-Chul, the name of this company means ‘three stars’ and began as a trading company in 1938. Since the 90s, it has evolved into a powerhouse with stakes in semiconductors, consumer electronics, insurance, and even food processing. It recently struck a massive deal involving $16.5B with Tesla. What company am I talking about?

A: Samsung

In July 2025, Samsung won a $16.5B contract to manufacture Tesla’s AI6 chips using 2 nm GAA (gate-all-around) transistors at its Texas fab. This massive foundry deal signals growing trust in its advanced-node readiness. While TSMC still leads in volume and yield, this contract represents a shift in competitive dynamics at the bleeding edge.

From Bloomberg: Samsung to Make Tesla AI Chips in Multiyear Texas Deal

#3

Used for growing single-crystal silicon, this method sounds almost like a ballet; slow pulling, precise rotation, and heat control are key. But beneath the elegance lies a flaw: if too much oxygen sneaks in, minority carrier lifetimes are degraded. What is this method called?

A: Czochralski Process

The Czochralski (CZ) method pulls a rotating seed crystal from molten silicon to grow large-diameter monocrystalline ingots. Crystal purity, defect density, and dopant uniformity are tightly controlled by atmosphere, temperature gradients, and rotation rates. It’s the dominant method for producing wafers used in both IC and photovoltaic industries.

See the Asianometry video on The Amazing Silicon Wafer. I also talk about this method in the article below.

#4

As gigawatt-class datacenters push towards higher DC voltages to boost efficiency, they flirt with a deadly risk: a breakdown of insulation that doesn’t just short — it detonates. We’re talking temperatures of 20,000°C — three times the sun’s surface temperature, vaporizing metal and unleashing explosive force. What’s the name of this catastrophic failure mode?

A: Arc Flash

An arc flash is a sudden, high-temperature electrical explosion caused by air ionization between conductors. It can reach temperatures of 20,000 °C, posing lethal risks. Causes include insulation failure, equipment damage, or human error. Mitigation involves proper labeling, PPE, arc-rated gear, and compliance with NFPA 70E standards.

From Wikipedia: Arc Flash. We also discussed this earlier in the context of high voltage DC architectures for GW-class datacenters.

#5

A new hyperscale datacenter project takes its name from a mythological figure who once defied the gods to deliver fire to humanity. What is this project called? Which company is building it?

A: Prometheus

Meta’s Prometheus campus in Ohio is a hyperscale AI data center designed to support large foundation models. It features high-density GPU clusters, liquid cooling, and a modular architecture to enable rapid deployment. It supports Meta’s push for 600,000+ GPUs across its “AI supercluster” network.

Read SemiAnalysis’ Meta Superintelligence – Leadership Compute, Talent, and Data.

#6

Which company, with the slogan “Eat Well, Live Well” originally known for its food additive business, became a critical supplier of films that were built on top of FR4 or glass core substrates and is a key material for advanced packaging of chips?

A: Ajinomoto

Derived from by-products of umami seasoning products and perfected in just four months, Ajinomoto Build-up Film (ABF) is a high-performance dielectric substrate used in advanced IC packaging for signal routing and insulation. It supports multilayer redistribution layers (RDLs), fine-line wiring, and low loss at high frequencies. ABF is essential for HPC, AI chips, and advanced 2.5D/3D packaging.

See Ajinomoto’s rather unconnected product offerings, read about ABF, and check out their interesting innovation story.

If you want to understand more about advanced packaging using ABF, see the post below.

#7

This type of Radar modulates the emitted signal frequency over time and uses the resulting beat frequency to extract both range and velocity simultaneously and is useful for automotive applications. What’s the name of this technique?

A: FMCW (Frequency-Modulated Continuous Wave)

FMCW radar transmits a continuously modulated frequency sweep. Mixing the received echo with the transmit signal yields a beat frequency proportional to distance, while Doppler shift reveals velocity. It enables fine resolution and low-power operation in automotive radar, presence detection, and mmWave sensors. Read more here.

#8

In the process of photolithography used to manufacture chips, these unique shapes are added to photomasks, but don’t print on the wafer. Their job is to shape the light field near edges, help resolve small features, and improve critical dimension. What are they called?

A: Sub-Resolution Assist Features (SRAFs)

SRAFs are non-printing optical features added near patterns to enhance lithography fidelity. They adjust the diffraction environment to improve critical dimension control. As patterning pushes below 10 nm, ML-assisted SRAF placement is becoming essential in OPC toolchains to minimize process variability. Read more about SRAFs here.

#9

Silicon is pretty great at a lot of things — even thinking — as we’ve recently seen with AI. Its greatest weakness is that it cannot produce light, while materials like Gallium Arsenide can. What is the property of silicon called that makes it its Achilles heel when it comes to producing light?

A: Indirect bandgap

Silicon's indirect bandgap prevents it from being an effective laser because the momentum of electrons and holes don't align, requiring a third particle—a phonon (lattice vibration)—to conserve momentum during recombination. This interaction makes the emission of a photon (light) a far less probable and efficient event compared to direct bandgap materials, where electrons and holes can recombine directly and emit light. Consequently, most of the energy in silicon is released as heat rather than light, making it unsuitable for the efficient light generation required for laser operation. Read more here.

#10

To minimize gate resistance and thermal noise in RF layouts, what process step is used to convert gate polysilicon in a MOSFET into a lower-resistance material?

A: Silicidation (Silicide or Salicide is also fine. The latter is short for self-aligned silicide)

Silicidation is a process in semiconductor manufacturing where a metal layer reacts with silicon to form a metal silicide. In MOS transistors, the polysilicon used in the gate often has a high resistance which translates to increased thermal noise. To minimize this contribution in circuits where noise matters, like in Low-Noise Amplifiers (LNAs), the polysilicon is silicided to reduce its resistance and its contribution to noise. Read more here.

Thanks for playing this week’s quiz!

If you enjoyed this post, share it with at least two people, and get a free month of paid subscriber benefits!

Share

Vik’s Newsletter

🍻 Semi Pub Quiz #1 Answers