The same cost and talent forces that once shifted chip manufacturing to Asia are now moving semiconductor design out of America, making India a powerhouse of design talent.
Hi Vik - I've greatly enjoyed your articles & perspective. One thing I feel you've overlooked in the "India is becoming the chip design capital of the world" discussion is ... education. Almost all of those "experts" in India have attended US universities ... what if the US increases the "tax" on Indians attending US universities? Will INdia continue to "build their expertise" without their students attending Cal, Stanford, Carnegie Mellon, MIT, et al??? Will their students still become experts despite being outside of the US academic community?
I believe that's what is coming next ... I can hear the admin's comments now "We cannot allow our country to educate/train a workforce only to see them return to their home countries". To date, it has worked because they stay in the US ... but you're proffering that the migration will now start, to which I disagree because of the education trump card (pun intended).
Universities are the key. Yes, India has several wonderful schools ... but, it'll take them 10-20 years to build the "academic community" that exists in the US. Where people study together, become friends, share career stories, help each other recruit, and most importantly, START startups ... I remember when Synopsys was 11 employees. Where are they now? I am not aware of a single startup in India - but that's likely my problem, not India's.
Keep on writing dude - this is excellent stuff and I appreciate the ability to interact, debate, decide, act based on your knowledge & expertise.
Yes, education is a key part of why chip design is doing so well in the US. pretty much in every country, there is now a push to develop more of a semiconductor trade school curriculum rather than advanced degrees, which really puts a high bar of entry for a lot of people who want to do semiconductors.
In the US and India, there are many programs that are allowing semiconductor concepts to be taught to a broader audience. Although it is true that chip design is a high-skill area, there are lots of parts of it that can be broken down into simpler tasks. Not all of it is entirely innovation-based. For example, amplifiers and communication systems are still the simple cascode circuit topology that was developed 40 years ago. It's just that we need hordes of designers to actually implement these circuits. I believe this can be taught relatively easily and does not need the high bar of education.
Even then, things are improving in India as evident from the amount of workforce offshored to India already.
Based on my limited observation, one thing that is a real and serious limitation is low per engineer productivity in India (given how much else they have to deal with outside their workplace) compared to say silicon valley levels of productivity. Cost will be time to market as you can't always keep throwing people to shorten the time.
Hey RK, I'm not sure that it is entirely an India-only problem. Having worked in both the US and India, I think the problems in each place are different, but they still exist. There is no clear productivity increase in one place over the other that I have seen.
Hi Vik, great write-up! One comment, one question:
Question is, what will be the likely impact of increased use of AI in chip design? By way of an example and AFAIK, Nvidia has invested substantial resources into using various forms of AI (from ML on up) for their own design process. Combined with continuing improvements of testing designs in simulations, this might be one of the areas where AI can really increase the productivity of their design teams.
2. The choice of the 180 nm process for the all-Indian chip for the satellite might also (mainly?) be to make the chip more resistant to ionizing radiation or easier to radiation-hardening it - a key requirement for use in space. As distances get really small, ionizing radiation is more likely to cause significant malfunctions . If you or someone else here knows what the currently smallest node for chips to be used in space are, please let me (us) know - Thanks!
Regarding AI in chip design, I think there is going to be a lot of positive impact because the design spaces in chip design (whether it's digital, analog, or anything in between) is enormous and navigating the space manually by human intuition and expertise is not efficient.
Rich Sutton's "bitter lesson" has taught us that when it comes to exploring large spaces (as in the case of Go or chess), brute computation through search and learning is always going to be the better approach. And the same thing applies to chips as well. When AI enters the world of chip design, there is going to be a lot of designs that emerge that have previously not been explored by humans.
Regarding 180nm for space applications, this is a very old technology and not entirely useful for a lot of applications that require any kind of cutting-edge performance. Even going to 90nm today isn't that small of a technology node and likely has no increased sensitivity to ionization mechanisms from space. Yes, sure, we won't be putting 3nm nodes up in space anytime soon. But there are many generations of technology that is still useful. It is interesting to know what the smallest node used in space applications currently is. I'll keep an eye out for this information.
Really fasinating analysis about India's emerging role in chip design. The Texas Instruments example you mentioned is particularly telling. I think the H1B visa changes are definetly accelerating this trend, and companies like TI are making the rational economic choice to move design work offshore. The talent pool in India is huge and the cost advantage is hard to ignore. I'm curious how this will affect the long term competitiveness of US chip companies, especialy if design expertise becomes concentrated overseas. Great writeup!
Hi Vik - I've greatly enjoyed your articles & perspective. One thing I feel you've overlooked in the "India is becoming the chip design capital of the world" discussion is ... education. Almost all of those "experts" in India have attended US universities ... what if the US increases the "tax" on Indians attending US universities? Will INdia continue to "build their expertise" without their students attending Cal, Stanford, Carnegie Mellon, MIT, et al??? Will their students still become experts despite being outside of the US academic community?
I believe that's what is coming next ... I can hear the admin's comments now "We cannot allow our country to educate/train a workforce only to see them return to their home countries". To date, it has worked because they stay in the US ... but you're proffering that the migration will now start, to which I disagree because of the education trump card (pun intended).
Universities are the key. Yes, India has several wonderful schools ... but, it'll take them 10-20 years to build the "academic community" that exists in the US. Where people study together, become friends, share career stories, help each other recruit, and most importantly, START startups ... I remember when Synopsys was 11 employees. Where are they now? I am not aware of a single startup in India - but that's likely my problem, not India's.
Keep on writing dude - this is excellent stuff and I appreciate the ability to interact, debate, decide, act based on your knowledge & expertise.
Dan Ganousis
Hey Dan, love your thoughts on this.
Yes, education is a key part of why chip design is doing so well in the US. pretty much in every country, there is now a push to develop more of a semiconductor trade school curriculum rather than advanced degrees, which really puts a high bar of entry for a lot of people who want to do semiconductors.
In the US and India, there are many programs that are allowing semiconductor concepts to be taught to a broader audience. Although it is true that chip design is a high-skill area, there are lots of parts of it that can be broken down into simpler tasks. Not all of it is entirely innovation-based. For example, amplifiers and communication systems are still the simple cascode circuit topology that was developed 40 years ago. It's just that we need hordes of designers to actually implement these circuits. I believe this can be taught relatively easily and does not need the high bar of education.
Even then, things are improving in India as evident from the amount of workforce offshored to India already.
Based on my limited observation, one thing that is a real and serious limitation is low per engineer productivity in India (given how much else they have to deal with outside their workplace) compared to say silicon valley levels of productivity. Cost will be time to market as you can't always keep throwing people to shorten the time.
Hey RK, I'm not sure that it is entirely an India-only problem. Having worked in both the US and India, I think the problems in each place are different, but they still exist. There is no clear productivity increase in one place over the other that I have seen.
Hi Vik, great write-up! One comment, one question:
Question is, what will be the likely impact of increased use of AI in chip design? By way of an example and AFAIK, Nvidia has invested substantial resources into using various forms of AI (from ML on up) for their own design process. Combined with continuing improvements of testing designs in simulations, this might be one of the areas where AI can really increase the productivity of their design teams.
2. The choice of the 180 nm process for the all-Indian chip for the satellite might also (mainly?) be to make the chip more resistant to ionizing radiation or easier to radiation-hardening it - a key requirement for use in space. As distances get really small, ionizing radiation is more likely to cause significant malfunctions . If you or someone else here knows what the currently smallest node for chips to be used in space are, please let me (us) know - Thanks!
Hey Peter, great questions!
Regarding AI in chip design, I think there is going to be a lot of positive impact because the design spaces in chip design (whether it's digital, analog, or anything in between) is enormous and navigating the space manually by human intuition and expertise is not efficient.
Rich Sutton's "bitter lesson" has taught us that when it comes to exploring large spaces (as in the case of Go or chess), brute computation through search and learning is always going to be the better approach. And the same thing applies to chips as well. When AI enters the world of chip design, there is going to be a lot of designs that emerge that have previously not been explored by humans.
Regarding 180nm for space applications, this is a very old technology and not entirely useful for a lot of applications that require any kind of cutting-edge performance. Even going to 90nm today isn't that small of a technology node and likely has no increased sensitivity to ionization mechanisms from space. Yes, sure, we won't be putting 3nm nodes up in space anytime soon. But there are many generations of technology that is still useful. It is interesting to know what the smallest node used in space applications currently is. I'll keep an eye out for this information.
Really fasinating analysis about India's emerging role in chip design. The Texas Instruments example you mentioned is particularly telling. I think the H1B visa changes are definetly accelerating this trend, and companies like TI are making the rational economic choice to move design work offshore. The talent pool in India is huge and the cost advantage is hard to ignore. I'm curious how this will affect the long term competitiveness of US chip companies, especialy if design expertise becomes concentrated overseas. Great writeup!