Huawei's Tau Scaling Is Really a Hybrid Bonding Bet
Tau Scaling is just extreme co-design and a hybrid bonding bet. The same “workaround” on a leading-edge node only widens the lead for those with EUV.
A lot of the news around Huawei’s “Tau Scaling Law” revolves around how China is circumventing EUV by optimizing on the time axis instead of the dimension axis. While this makes for headline bait, the engineering behind Huawei’s approach is how they optimize the system for best performance and not just the transistor size.
This can be done across many axes, with: hybrid bonding for advanced packaging, Unified Bus for memory protocols, near-packaged optics for interconnects and software optimizations overall. We will just focus on the transistor layer here, and address the question: What if the route to leading-edge density did not require a leading-edge transistor at all, but instead came from folding a 7nm-class design back on top of itself until the footprint density rivals a node three years ahead? This is what Huawei calls LogicFolding.
In this post, we will discuss:
What Tau Scaling and LogicFolding actually are: chasing time as an axis instead of scaling dimension.
Why hybrid bonding is the hard part: the challenges that decide whether fine-pitch logic stacking actually yields.
Who builds the bonders: the short, concentrated supply chain and why its geography matters for China.
How far along China’s own bonder makers are: Where is the current capability, and the gap that still leaves.
What it means for the US lead: why the same stacking on an EUV-class node widens the gap instead of closing it.
If you need a refresher on hybrid bonding, see earlier post below.
We also have a deep dive on lithography on the Semi Doped podcast. See it on YouTube.
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Tau Scaling and LogicFolding
Huawei’s Tau Scaling takes its name from the Greek Letter τ, which represents the delay through a signal path. Historically, making transistors smaller and faster has reduced this delay. But past the 7nm node, making the delay smaller has become increasingly difficult without the use of EUV lithography, which China does not have access to due to export control laws.
Huawei’s solution is practically sound: if you can’t improve the signal delay through the transistor without EUV, why don’t we optimize everything else we can? Their goal is to shrink that delay across four levels at once: the device, the circuit, the chip and the full system.
At the chip level, the way to do this is to take a chip built on a trailing DUV node, like SMIC’s 7nm-class process (incidentally, Huawei has never named the foundry, but everyone assumes it is SMIC). If you can stack logic chips built on this one on top of the other and hook them up, you’ve just doubled transistor density without EUV. Think of it like printing two chips on a napkin, and folding them in half so that they align, and then hooking them up. This is what Huawei calls LogicFolding, and hooking them up requires a packaging technology called hybrid bonding.
By folding chips like a taco, you’ve just reduced the interconnect distance massively, and the unwanted resistance and capacitance that come from longer wiring is dramatically reduced. This makes the silicon run faster with lower delay, and Huawei has effectively made chips faster and denser by stacking them on top of each other.
Huawei reports the Kirin 2026 part, its first LogicFolding product shipping in fall 2026, moving from 155 to 238 MTr/mm² of transistor density (roughly +53.5%), alongside a 41% gain in performance-core power efficiency and a clock bump to 3.1 GHz. The caveat here that many experts are pointing out is that Huawei spent twice the amount of silicon to double the transistor density, which is not the same as using EUV to make denser transistors.