Why Building Smarter EDA Tools Is Key To Winning The AI Era
If AI is the gold prize, AI-enabled EDA tools are the picks and shovels. Why traditional chip design tools are stuck in the past, and how new AI-first EDA approaches could be critical to the AI boom.
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“You can either mine for gold or you can sell pickaxes.”
As the story goes, businessmen like Levi Strauss built their fortunes not by chasing gold themselves, but by supplying the miners with the tools, services, and infrastructure they needed during the California gold rush.
Today, it’s clear that platforms like YouTube and Netflix have won the online video race. But Akamai quietly built a strong business selling the infrastructure that made those services possible. Their work in content delivery networks, edge computing, and security formed a large part of the backbone of the internet. As a result, Akamai ended up with a well-diversified business that delivered consistent profits.
The current semiconductor boom is laser-focused on building the best chips for AI training and inference. This has pushed Nvidia to the brink of becoming the world’s first four trillion dollar company, while AMD is closing the gap with impressive progress of its own. At the same time, players like OpenAI, Meta, and others are chasing the ultimate prize: artificial superintelligence. The AI gold rush is clearly on, with top AI researchers getting multi-million dollar pay packages.
One of the many picks and shovels in the AI race is electronic design automation (EDA) tools — an industry that will thrive regardless of who wins the chips race. The premise is that companies with the best AI tools will be able to make better chips faster than their competition with fewer people. Today, semiconductor companies can only dream to drive up revenue per employee to the levels of OnlyFans.
In this post, we will discuss the AI-ification of EDA tools and how those building chip infrastructure will see long-lasting opportunity.
A Rapid Walk through EDA History: If you’re new to EDA, this section provides historical context to how we got here today. The evolution of the tools used in chip design are discussed briefly.
AlphaChip and LLMs in Chip Design: Ever since Google demonstrated success in using reinforcement learning for CPU design, there has been rising interest in the use of LLMs for chips with traditionally software-centric incubators like Y-Combinator jumping into hardware.
The Main Issue with EDA Tools: EDA tools have not evolved with chip technology; ask any design engineer and they’ll tell you they’re stuck in the ‘90s. We will discuss why this is the case.
The Rise of AI-Native EDA: When AI becomes the focal point in engineering conferences and chip corporations, it is a signal of things to come and where opportunities lie in the future.
🔒For paid subscribers:
The “Picks and Shovels” opportunity: How startup and established EDA companies should look at enabling AI in the chip design flow, and five areas in chip design that are ripe for AI EDA disruption.
Risks and Barriers: Four likely obstacles that EDA companies will encounter when deploying AI in the semiconductor design industry.
30+ AI-Native EDA Startups That Are Emerging For Semiconductor And Chip Design: A comprehensive table that lists emerging AI-native startups and what they are working on. Google Sheets link provided.
Read time: 15 mins
A Rapid Walk Through EDA History
To appreciate what EDA tools do today, it helps to look back. Early chip layouts were drawn by hand on graph paper, then transferred to Rubylith film to make photomasks. Mask cutters would crawl over giant tables to cut patterns, carefully avoiding damage to the film. Asianometry has a great video on this.
Those early hand-crafted layouts eventually powered computers that helped design the next generation of chips, starting the self-reinforcing cycle of computers building faster computers. IBM began exploring computer-aided design in the late 1950s, initially to help document, display, and check circuit schematics. Mask pattern generation would follow later.
By the 1970s, most chip projects depended on Calma’s Graphical Design System (GDS), whose 1978 successor GDS-II became the layout data standard still in use today. In those early days, design was mostly led by device physicists with limited experience in large-scale circuit architecture. As transistor counts grew past 10,000, Lynn Conway and Carver Mead’s Introduction to VLSI Systems connected circuit design with practical, scalable layout methods, enabling system designers to directly engage in chip design. That laid the groundwork for the modern EDA field.
The 1980s saw the rise of companies like Mentor Graphics (1981) and Cadence Design Systems (1988), along with Synopsys (founded 1986 and becoming prominent in the early 1990s). Logic synthesis was a major leap, letting designers move from high-level hardware description languages straight to gate-level netlists. Automated place-and-route could then connect millions of transistors while optimizing power, performance, and area.
After 2000, chips became too complex for traditional gate-level methods alone. Designers needed higher abstraction, which brought high-level synthesis and system design languages. As densities grew, power, thermal, and signal integrity checks became vital. In the last decade, advanced packaging has pushed EDA tools to handle 3D-ICs, chiplets, and wafer-scale systems, expanding the challenge from transistors all the way to assembly and interconnects.
Modern chips take years to develop and require hundreds of engineers. The design space is enormous. Today, AI and machine learning are being woven carefully into EDA workflows to accelerate design and improve accuracy, but they still rely heavily on expert guidance. If you’re interested in a deeper dive into EDA — I recommend Chip Insights’ 3-part series covering the history, open-source, and AI-era of EDA.
AlphaChip and LLMs for Chip Design
The strongest push for AI in chip design comes from Google’s AlphaChip. This reinforcement learning agent automates the floor planning of chips, a task traditionally handled by experienced engineers.
AlphaChip is pre-trained on layouts for network chips, memory blocks, and data-transport buffers, and then applied to Google’s own designs, including the latest Trillium TPU and their ARM-based Axion processors for data center CPUs. According to an estimate by Devansh on Substack, AlphaChip could save as much as $3.6 million per chip in design costs.
However, when LLMs first showed they could write software code, it was natural to try and apply it to RTL code in digital chip design. In 2024, Y Combinator took that idea further by putting out a request for startups focused on applying LLMs to chip design. That move turned the spotlight onto hardware in a way usually reserved for software.
But anyone who has spent time in this industry knows that bringing LLMs into a domain as intricate and detail-heavy as chip design is far from simple. As Zach writes in his article on why YC is wrong about LLMs in chip design,
If Gary (sp.) Tan and YC believe that LLMs will be able to design chips 100x better than humans currently can, they’re significantly underestimating the difficulty of chip design, and the expertise of chip designers.
Chip design has always leaned on a lot of tacit knowledge — the kind you pick up over years on the job and can’t easily write down. Still, there’s a strong pull to get as much AI into the design flow as possible. EDA tools have looked stuck in the 1990s for what feels like forever, and it’s not just the dated interfaces that bother people. The amount of manual, repetitive work in chip design is huge, and everyone can see the need for more intelligent, automated ways to get things done.
The Main Issue with EDA Tools
For anyone who has worked in the semiconductor industry, it is clear that the day-to-day EDA tools feel extremely behind modern software standards. There are good reasons why this is so:
Fabless semiconductor companies have a lot of sunk cost into building up design infrastructure. They don’t want to migrate databases to a newer platform.
The risk of design data migrations being incorrect has too great of a cost on revenue considering delays, hours of effort tracking down bugs, and potentially resulting in chip failures.
Big EDA companies have no incentive to rewrite their tool interfaces from the ground-up, and seasoned veterans in the industry are happier with what they know.
The Big Three1 of EDA have 90%+ market share across the industry that is hard to displace. EDA startups usually end up getting acquired or sued.
Due to the ancient workflows used in chip companies, there is an enormous amount of manual effort in setting up testbenches, schematics, and layouts. There are also limited tools to explore and debug design spaces that are getting exponentially larger with the added complexity of leading edge technologies, chiplets, and advanced packaging. This also means that it is harder to find costly mistakes that can be life or death for small- to mid-sized fabless companies.
The lack of cutting edge tooling makes it hard to generate the best possible chip designs. Design cycles are often constrained by tight tapeout deadlines, which limits the number of design iterations can be done performed before tape-out. As a result, designers frequently have to settle for suboptimal choices in the interest of time.
The Rise of AI-Native EDA
The Big Three EDA companies all have released products that have AI/ML approaches incorporated into their workflow. Synposys DSO.ai, Cadence.AI, Siemens EDA AI, and Ansys AI+ are all suites of applications that incorporate intelligence into conventional design flows. There is a flurry of recent EDA startups trying to incorporate agentic AI methods into chip design. We will look at some of these later.
The 62nd Design Automation Conference2 held in San Francisco recently was all abuzz with talk of agentic approaches to chip design. The entire show seemed completely AI-centric, with a significant focus on design verification — a time-consuming task which is recently in high demand due to the rise of accelerator chips, but for which talent is scarce. There was lots of chatter about agentic RTL code generation, waveform debugging, and PPA estimation. The IEEE International Conference on LLM-Aided Design is also a forum entirely dedicated to AI-native chip design.
There is also a slew of AI-enabled PCB design tools from major EDA companies like Zuken and Altium, the latter of which was acquired by Renesas in 2024 for $5.9 billion. The portfolio of Altium products will be launched as Renesas 365, an online platform for electronics system development that will easily integrate with their product portfolio.
There is big potential and payouts for EDA tools that solve the right problems in the industry — with or without AI.
Beyond the paywall we will delve deeper into the AI-ification of EDA tools by looking at the following.
Market opportunities and challenges: What makes EDA a “picks and shovels” market, where the opportunities lie, how it benefits the chip industry, and the risks and barriers involved.
A detailed list of 30+ AI-native EDA startups who are focusing on the use of AL/ML or LLMs for ASIC/FPGA design, mixed-signal, RF/analog, PCB and testing validation, which provides stats such as founding year, funding stage, unique selling proposition, and more.