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Semiconductor Devices and Fabrication

High Stakes Advanced Node Poker: TSMC Goes All-in, Intel Folds
Understanding the insatiable demand for TSMC advanced nodes and packaging, Intel’s bleak results, the saving grace of EMIB, and the $11B CPU fumble, and…
 • Vikram Sekar
2025 International Electron Devices Meeting (IEDM): Detailed Conference Report
Coverage of the world's premier conference on semiconductor devices.
 • Vikram Sekar
2:33
NVIDIA CuLitho and the Future of Inverse Lithography
How GPU-scale compute is reshaping mask synthesis for advanced nodes.
 • Vikram Sekar
Why Citing Yield Without Die Area is Meaningless
Pat Gelsinger's field notes, and how defect density is a more meaningful metric for yield.
 • Vikram Sekar and Jack Huang
How Dennard Scaling Allowed Transistors to Shrink
A detailed explanation of Robert Dennard's exact rules to scale a MOS-transistor's dimensions that resulted in more transistors on a single chip without…
 • Vikram Sekar
Ruthenium: The Next Step in Interconnects for Advanced Logic Nodes?
Why ruthenium is emerging as an alternative to copper for low-level metal interconnects as pitch drops below 20-nm in sub 2-nm class advanced technology…
 • Vikram Sekar
How Foundries Calculate Die Yield
Understanding the metric that Intel used to abandon a whole technology node.
 • Vikram Sekar
Understanding Compact Models for MOS and Bipolar Devices
Looking under the hood of your schematics.
 • Vikram Sekar
A Guide to Noise Sources in MOS Transistors
Noise is the great limiter. Without it, we could communicate over arbitrarily large distances while consuming almost no power. Unfortunately for us mere…
 • Vikram Sekar
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