Semiconductor Devices and Fabrication

NVIDIA CuLitho and the Future of Inverse Lithography

How GPU-scale compute is reshaping mask synthesis for advanced nodes.

Mar 30 •

Why Citing Yield Without Die Area is Meaningless

Pat Gelsinger's field notes, and how defect density is a more meaningful metric for yield.

Feb 16 •

and

How Dennard Scaling Allowed Transistors to Shrink

A detailed explanation of Robert Dennard's exact rules to scale a MOS-transistor's dimensions that resulted in more transistors on a single chip without…

Jan 12 •

Ruthenium: The Next Step in Interconnects for Advanced Logic Nodes?

Why ruthenium is emerging as an alternative to copper for low-level metal interconnects as pitch drops below 20-nm in sub 2-nm class advanced technology…

Jan 5 •

How Foundries Calculate Die Yield

Understanding the metric that Intel used to abandon a whole technology node.

Sep 15, 2024 •

Understanding Compact Models for MOS and Bipolar Devices

Looking under the hood of your schematics.

May 12, 2024 •

A Guide to Noise Sources in MOS Transistors

Noise is the great limiter. Without it, we could communicate over arbitrarily large distances while consuming almost no power. Unfortunately for us mere…

Mar 10, 2024 •

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