Sitemap - 2025 - Vik's Newsletter
A Detailed Playbook to Leveling Up Your Meetings, Mentorship, and Career Conversations
Passion versus Practicality in Engineering Careers
Why Building Smarter EDA Tools Is Key To Winning The AI Era
How Cracked Engineers Recreated World-Class RF Research in 30 Hours on Social Media
IMS 2025: AI for RF, Heterogenous Integration, 100 GHz+ Systems, RF GaN
Has RF Lost Its Spark? Rethinking Innovation in the AI Era
IMS 2025: Why LEO Satellite Markets Are Brutally Exclusive and What to Do About It
7 Unwritten Rules for High-Impact Engineering Careers
Using AI to Break the Black Magic of RF Design
A Comprehensive Primer on Advanced Semiconductor Packaging
Upcoming Long Post, Summer of Protocols Talk, 2025 International Microwave Symposium
Why Earth's Best Optical Fiber Can Only Be Made in Space
How Edge-AI Chips can Solve the Cocktail Party Problem
Why Getting a Semiconductor Job Is Harder Than It Should Be
Why 50 Ohms Became the RF Standard
A Comprehensive Guide To Installing Open Source Tools For Integrated Circuit Design
Carrier Diffusion, Generation and Recombination in Semiconductor Devices
SiliWiz, Short Posts, and Discount Plans
How to Learn Chip Design With Open-Source EDA Tools
Why the Chip Industry Is Struggling to Attract the Next Generation
Can You Vibe Your Way Through Chip Design?
The Engineer’s Guide to Measurement Precision
NVIDIA CuLitho and the Future of Inverse Lithography
How Electrons Move in Semiconductors: The Science of Carrier Drift
The Silicon Photonics Moonshot: Group IV Integrated Lasers
Why Fathom Light uses LiDAR in Long Range Airborne Applications
The Gigabit Wall: No More Need for Speed
First Impressions from 2025 ISSCC
Why Citing Yield Without Die Area is Meaningless
The Rise of 800V Electric Vehicles and Role of Silicon Carbide
Semiconductor Doping, Electron Affinity, Work Function and Anderson's Rule
Understanding Energy Bands in Semiconductors
The Joy of Semiconductor Devices
January 2025: Margin Notes on Optics
How Dennard Scaling Allowed Transistors to Shrink
Ruthenium: The Next Step in Interconnects for Advanced Logic Nodes?